• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.149-158
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• 2007

A In the rapidly changing media environment, radio needs to be digitized in order to provide regular compatible service. Especially, most medium high frequency Medias have program contents thar are similar to the standard FM bandwidth, so digitizing radio will bring less effect than it is expected. However, the characteristics of radio medias are mobility, individuality, site-to-site, wide service coverage, immediate delivery and publicity, so it is necessary to study the future of radio media to provide continuous services, moreover, the main discussion regarding balanced development between medias will be the trend of the digitization of radio. Also it is easy and will cost less to change compared to other medias. AM was the first media to broadcast in Korea, and its network is spread all over Korea, also the receivers are the most widely distributed which means the signal reaches everywhere in Korea. In this study, the proper service model for AM digital radio is provided in this environment in which all Medias are rapidly digitizing due to the advancement of digital technology. The results of experimental are based on library study and KBS data of sound wave.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.77-84
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• 2000

In this paper, we discuss a symbol clock extraction scheme based on maximizing the band-edge component of the transmitted signal frequency spectrum for applications to 51.84Mbps VDSL system which uses a 16-QAM. The major characteristics of the digital PLL are examined. In addition, we suggest an efficient design method of a sinusoidal look-up table which is used for NCO.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.417-426
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• 2000

In this paper, CE-CPSK(Constant Envelope Continuous Phase Shift Keying) modulated DS/SS(Direct Sequence Spread Spectrum) transceiver with 908 MHz carrier frequency and 1.5 MHz PN clock rate is proposed. To overcome the effect of nun-linear power amplifier, CE-CPSK modulation method which has the constant envelope and continuous phase characteristics is proposed. To analyze the DS/SS receiver performance with respect to code tracking loop, multipath fading channel is characterized as a two-ray Rayleigh fading channel. To compensate the demerit of analog delay locked loop, digital delay locked loop is employed for code tracking loop. Simulation and experimental examination has been carried out in AWGN(Additive White Gaussian Noise) and Rayleigh fading channel environment in order to prove validity of the proposed method.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.101-104
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• 2001

In this paper, we propose the Digital Automatic Gain Controller for IEEE 802.11a High-speed Physical Layer in the 5 GHz Band. The input gain is estimated by calculating the energy of the training symbol that is a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.71-76
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• 2001

In this paper we propose the Digital Automatic Gain Controller for IEEE 802.11a-High-speed Physical Layer in the 5 GHz Band. The input gain it estimated by calculating the energy of the training symbol that it a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• The Journal of the Convergence on Culture Technology
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• v.7 no.3
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• pp.565-570
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• 2021

A soft-decision decoding scheme of a channel code for correcting an error occurring in a receiver of a digital communication systems is proposed. A method for efficiently decoding by use of the linear and arithmetic structure of linear block codes is presented. In this way, the probability of decoding errors has been reduced. In addition, it is possible to reduce the complexity of decoding as well. Sufficient conditions for achieving optimal decoding has been derived. As a result, the sufficient conditions enable efficient search for candidate codewords. With the proposed decoding scheme, we can effectively perform the decoding while lowering the block error probability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7A
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• pp.725-730
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• 2010

Preparing the conversion to the digital broadcasting system, we are deciding broadcasting network plan and interference protection area, using the measured receiving electric field level from the digital broadcasting station. However, the essential researches are needed about a receiving electric field level, because a digital TV (DTV) broadcasting receiver has been improved and an actual receiving environment should be considered. In this paper, the measured data were classified with domestic terrain of line of sight (LOS) and those of non-LOS, and effective receiving electric field level was proposed based on the LOS data. It is known that receiving electric field-level of 48 ㏈uV/m or more should be required for receiving rate of 90% and 50 ㏈uV/m for that of 95%, on the basis of the information of domestic terrain LOS.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.1
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• pp.45-50
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• 2012

In the current wireless communication technology, the digital radio system replaces the analog radio broadcasting. Since the in-band digital radio systems are used in the existing analog radio frequency band, interference problems of digital radio are caused. It is important to effectively analyze the interference. In this paper, to analyze SINR and BEP (bit error probability) of digital radio system, we propose the analysis method considering angular effect. The angular effect means a method to analyze the interference when the receiver is located in different directions around the transmitter. These results are able to give basic information for the allocation of digital radio networks.

• Journal of Digital Contents Society
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• v.16 no.1
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• pp.71-77
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• 2015

Currently, numerous (broadcasting) programs are being provided to viewers, which makes it hard for viewers to select a program to watch. Especially, surfing channels watching the program videos (which is the most general manner of searching a program) became a time consuming task of performing several tens of channel changes (a channel change takes about 0.7 second). In the paper, a data service for guiding programs using the multi-view of program videos is proposed. The data service allows viewers to navigate all program videos without channel changes. To implement the data service, a method for composing and transmitting multi-view videos with the meta data for handling each video of the multi-view has been devised and a Java API has been implemented to clip, resize, and display parts of the multi-view videos.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.