• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.10
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• pp.691-699
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• 2014

In order to increase network lifetime, duty-cycle MAC protocols which can reduce energy consumption caused by idle listening is proposed for WSNs. In common duty-cycle MAC protocols, each sensor node calculates its duty-cycle interval based on the current amount of residual energy. However, in WSNs with the capability of energy harvesting, existing duty-cycle intervals based on the residual energy may cause the sensor nodes which have high energy harvesting rate to suffer unnecessary sleep latency. Therefore, a duty-cycle scheduling scheme which adjust the duty-cycle interval based on both of the residual energy and the energy harvesting rate was proposed in our previous work. However, since this duty-cycle MAC protocol overlooked the performance variation according to the change of duty-cycle interval and adjusted the duty-cycle interval only linearly, the optimal duty-cycle interval could not be obtained to meet application requirements. In this paper, we propose three methods which calculate the duty-cycle interval and analyse their results. Through simulation study, we verify that network lifetime, end-to-end delay and packet delivery ratio can be improved up to 23%, 44% and 31% as compared to the existing linear duty-cycle scheduling method, respectively.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.320-322
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• 2013

무선센서네트워크에서 MAC 프로토콜은 듀티사이클을 이용하여 센서노드의 에너지 소비를 줄임으로써 배터리의 수명을 연장한다. 기존에 제안된 TA (Traffic-Adaptive)-MAC 프로토콜은 비동기 방식 기반으로 듀티사이클을 조절하여 센서노드의 에너지 소비를 줄인다. 본 기법은 네트워크의 트래픽 상태를 고려하여 동적으로 센서노드의 듀티사이클을 조정한다. 이러한 방법으로 센서노드의 대기시간을 줄이고 센서노드의 에너지를 효과적으로 사용한다. 하지만 이 기법은 네트워크의 트래픽 변화가 잦은 환경에서는 좋지 못한 효율을 보인다. 따라서 본 논문에서는 기존의 TA-MAC 기법에 가중이동평균 방법을 적용하여 합리적인 듀티사이클 선정을 위한 트래픽 계산 방법을 제안한다. 이는 최근 트래픽 값과 현재 감지한 트래픽의 평균을 계산하고 다음 트래픽을 예측하여 네트워크 트래픽이 급격히 변화하는 불안정한 환경에서 더 합리적인 듀티사이클 선정을 돕는다.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.252-253
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• 2017

본 논문에서는 벅-타입 능동 전력 디커플링 회로의 새로운 듀티 사이클 생성 방법을 제안한다. 기존의 듀티 사이클 생성방법에 비해 단순해진 듀티 사이클 계산 방식은 저성능 마이크로 프로세서에도 적합함과 동시에 보다 효과적으로 능동 전력 디커플링 회로를 제어할 수 있다. 제안하는 회로는 전류 불연속 모드로 동작하며, 전류 지령치는 DC링크 전류의 1차 리플 성분에 전류 이득을 보상하여 생성하기 때문에 모든 구간에서 효과적으로 DC링크의 전압 리플을 줄일 수 있다. 제안하는 듀티 사이클 생성 방법의 효과는 MATLAB-Simulink을 통해 검증하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.142-147
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• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.193-198
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• 2016

For environmental monitoring and risk identification of industrial plants, several monitoring systems using Wireless Sensor Networks (WSNs) have been developed. In this paper, we propose a dynamic duty cycle adjustment mechanism for reduced latency in industrial plants. The proposed method adjusts the duty cycle among predefined risk groups depending on the urgency of sensed data values. To demonstrate its efficacy, we analyze the expected transmission latency model and then discuss the characteristics in detail. We show that the proposed dynamic duty cycle mechanism is a more effective than a periodic mechanism by analyzing the expected latency of them in industrial plants where there are various types of sensory data with different levels of reliability.

• Journal of Software Assessment and Valuation
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• v.15 no.1
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• pp.103-107
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• 2019

Recently, many technologies have been developed to realize low power high speed digital data communication and one of them is related to duty cycle correction. In this paper, a low-area duty cycle correction circuit for a voltage-controlled ring generator is proposed. The duty cycle correction circuit is a circuit that corrects the duty cycle using a 180 degree phase difference of a voltage controlled ring oscillator. The proposed low-area duty cycle circuit changes a conventional flip-flop to a true single phase clocking (TSPC) flip-flop And a low-area high-performance circuit is realized. By using TSPC flip-flop instead of general flip-flop, it is possible to realize low-area circuit compared to existing circuit, and it is expected to be used for high-performance circuit for low-power because it is easy to operate at high speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1B
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• pp.154-161
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• 2010

In wireless sensor networks, due to the many-to-one convergence of upstream traffic, congestion more probably appears. The existing congestion control protocols avoid congestion by controlling incoming traffic, but the duty-cycle operation of MAC(Medium Access Control) layer has not considered. In this paper, we propose DCA(Duty-cycle Based Congestion Avoidance), an energy efficient congestion control scheme using duty-cycle adjustment for wireless sensor networks. The DCA scheme uses both a resource control approach by increasing the packet reception rate of the receiving node and a traffic control approach by decreasing the packet transmission rate of the sending node for the congestion avoidance. Our results show that the DCA operates energy efficiently and achieves reliability by its congestion control scheme in duty-cycled wireless sensor networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.395-402
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• 2008

In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duksty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process and dissipates 184mW at 1.8V single supply The SNDR of the proposed 12bit ADC is 52dB and SFDR of 59dBc(@Fs=20MHz, Fin=1MHz) is measured.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.9-15
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• 2009

In this paper, we invented a new structure of fast ATC(Automatic Threshold Control) circuit. Using the structure we made a new burst-mode limiting amplifier with fast ATC function using commercial $0.8{\mu}m$ BiCMOS technology. It's ATC function worked so fast that even the first bit of burst-data could be detected, which confirmed that the new structure was useful for fast ATC. However, in the beginning of a burst, distortions in duty-cycle occurred and increased up to 59% of duty-cycle as amplitude of input signal increased. But we confirmed that after 10 cycles passed, duty-cycles was staying below 52% of duty-cycle for any magnitude of input signal.