• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.4
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• pp.100-108
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• 1997

A combined buck and boost push-pull quantum series resonant rectifier(PPQSRR) is newly proposed to achieve a power factor correction without start-up inrush current. Based on the developed dynamic modeling of the proposed rectifier, an inrush current elimination control technique is proposed and the usefullness of the proposed rectifier and control method are verified by computer simulation and experimental results. With the proposed control method, a high power factor and wide range of output voltage can be obtained.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.5
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• pp.397-404
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• 1999

In this paper, several control methods for the discontinuous mode PWlvl-SRC are investigated with the l linearized small signal model. In order to analyze the stability and dyncunic characteristics of the controlled s system, the root locus as a function of the normaliz떠 output current(]\iOC) for a given normalized output v voltage(NOV) is employed. FurLhem10re, in this paper, the “Optimal trajectory control of PWM-SRC" is newly p propos(xl and its good dvnamic performances are evaluated with other four control laws.laws.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.41-47
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• 1998

We propose a new high speed and low power SOI inverter with dynamic threshold voltage that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.1824-1825
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• 2006

항공기, 차량, 유도탄 등과 같은 동적인 플랫폼에서 표적을 추적하기 위해서는 시선을 안정화하는 외부의 추적루프와 내부의 속도 루프를 포함하는 서보 구조가 필요하다. 본 논문에서는 내부의 속도 루프인 안정화 루프에 큰 입력 전압이 인가되었을 때 구동기(Actuator) 포화 현상에 의해서 공간 안정화 루프 성능이 나빠지지 않게 와인드업 방지(Anti-windup) 기능을 가진 디지털 비례적분(Proportional Integral, PI) 제어기를 설계한다. 디지털 와인드업 방지 비례적분 제어기는 일반적으로 SISO 시스템 설계를 위한 방법으로 와인드업 방지 기능을 가진 R, S, T 다항식으로 표현되는 입출력 형태의 제어기를 이용하여 설계하였다. 설계된 제어기는 모델링에 의한 시뮬레이션 결과와 실험결과를 통해 성능을 분석하였다.

• Proceedings of the KIEE Conference
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• 2001.11b
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• pp.259-262
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• 2001

본 논문은 2003년 한전 실계통(154kV 강진 S/S)에 적용예정인 80MVA UPFC(Unified Power Flow Controller)시스템의 동적특성을 EMTDC/PSCAD를 이용하여 분석한 결과이다. UPFC는 FACTS 기기중 전압, 임피던스, 위상각등 전력전송 제어를 위한 송전선로의 모든 파라미터를 동시에 독립적으로 제어 할 수 있는 FACTS기기[1]로서, 미국 Inez S/S, Marcy S/S에 이어 강진 S/S에 80MVA 용량의 UPFC가 실계통 적용될 예정이다. 본 논문은 과도현상 해석 프로그램인 PSCAD/EMTDC를 이용하여 80MVA UPFC 제어기와 적용 대상 계통인 강진 S/S 인근 계통을 모델링하고 상정사고에 대한 UPFC 제어효과 분석에 대하여 기술하였다. 적용된 EMTDC UPFC모델은 실제 80MVA UPFC 기기에 채용된 전력회로, 제어기, 보호시스템과 동일하게 모델링하였으며 적용 대상계통은 PSS/E 해석결과와 동일하도록 강진 S/S인근 계통을 축약 등가화한 계통모델을 사용하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.3
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• pp.204-210
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• 2009

This paper proposes a novel current-sensorless maximum torque per ampere control for a surface mounted permanent magnet synchronous motor with low-resolution position sensor. A direct axis current is estimated from the mathematical model of the permanent magnet synchronous motor and the phase angle between direct and quadrature axis voltage commands is controlled to adjust the estimated direct axis current to zero, thus a maximum torque per ampere control can be achieved. The proposed method is suitable for low cost applications with slow dynamic response characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.15-24
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• 2012

In this paper, we suggest the dynamic-response-free SMPS using a new high-resolution DPWM generator based on switched-capacitor delay technique. In the proposed system, duty ratio of DPWM is controlled by voltage slope of an internal capacitor using switched-capacitor delay technique. In the proposed circuit, it is possible to track output voltage by controlling current of the internal capacitor of the DPWM generator through comparison between the feedback voltage and the reference voltage. Therefore the proposed circuit is not restricted by the dynamic-response characteristic which is a problem in the existing SMPS using the closed-loop control method. In addition, it has great advantage that ringing phenomenon due to overshoot/undershoot does not appear on output voltage. The proposed circuit can operate at switching frequencies of 1MHz~10MHz using internal operating frequency of 100 MHz. The maximum current of the core circuit is 2.7 mA and the total current of the entire circuit including output buffer is 15 mA at the switching frequency of 10 MHz. The proposed circuit has DPWM duty ratio resolution of 0.125 %. It can accommodate load current up to 1 A. The maximum ripple of output voltage is 8 mV. To verify operation of the proposed circuit, we carried out simulation with Dongbu Hitek BCD $0.35{\mu}m$ technology parameter.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.1
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• pp.1-8
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• 2008

A dynamic model for II-SEPIC(Isolated Inverse-SEPIC) is developed based on the state-space averaging method and its control characteristics are investigated in this paper. Equations for circuit design of II-SEPIC are derived through steady state analysis and the resulted circuit parameters are used in the consequent simulation and experiment works. A structure of control system is devised to obtain better control performance. In order to verify validity and effectiveness of the design equations and dynamic model derived, dynamic control responses of II-SEPIC system against line and load variation are illustrated in both simulation and experiment.

• The Transactions of the Korean Institute of Power Electronics
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• v.2 no.4
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• pp.28-35
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• 1997

본 논문에서는 송전선로에 직렬로 삽입되어 선로의 리액턴스를 동적으로 보상하는 인버터식 직렬보상기에 대한 동적 응동 해석을 기술하고 있다. 이 직렬보상기는 다중펄스로 동작하는 전압원인버터와 결합변압기, 그리고 제어장치로 구성되어 있으며, 점호각을 조절하여 선로의 리액턴스를 가변하고 용량성 뿐만 아니라 유도성 보상도 가능하다. 이 보상기로 선로의 리액턴스를 감소시키면 전송 유효전력의 증각가 가능한데, 이러한 효과를 본 논문에서는 단일기-무한대-버스 전력계통에 대해 EMTP를 이용한 시뮬레션으로 확인하였으며, 또한 축소모형 제작과 실험을 통해 실험적으로 확인하였다.