• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.59-64
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• 2002

In the RFID system using ISM-band, The tag mounted at the object has used the DC power by rectifying the RF signals of the small antenna for operating the micro-controller and memory. The performance of the tag would be reduced because of the second harmonics generated by the nonlinearity of the semiconductor and the spurious signal excited the high order mode of the antenna. This paper has realized the novel type low-pass filter with "the Stub-I type DGS slot structure" to improve the efficiency of the tag by suppressing the harmonics. The optimized frequency character at the pass-band/stop-band has obtained by tuning the stub width and slit width of I type slot. The measured result of the LPF has the cutoff frequency 3.25 GHz, the insertion loss about -0.29~-0.3 dB at pass-band 2.4 GHz~2.5 GHz, the return loss about -27.688~-33.665 dB at pass-band with a good performance, and the suppression character is about -19.367 dB at second harmonics frequency 4.9 GHz. This DGS LPF may be applied the various application as the RFID, WLAN to improve the efficiency of the system by suppressing the harmonics and spurious signals. 

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1154-1162
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• 2016

This paper proposes a fast-transient digital LDO(Low dropout) regulator with binary-weighted current control technique. Conventional digital LDO takes a long time to stabilize the output voltage, because it controls the amount of current step by step, thus ringing problem is generated. Binary-weighted current control technique rapidly stabilizes output voltage by removing the ringing problem. When output voltage reliably reaches the target voltage, It added the FRZ mode(Freeze) to stop the operation of digital LDO. The proposed fast response digital LDO is used with a slow response DC-DC converter in the system which rapidly changes output voltage. The proposed digital controller circuit area was reduced by 56% compared to conventional bidirectional shift register, and the ripple voltage was reduced by 87%. A chip was implemented with a $0.18{\mu}F$ CMOS process. The settling time is $3.1{\mu}F$ and the voltage ripple is 6.2mV when $1{\mu}F$ output capacitor is used.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.651-659
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• 2010

In this paper, a new six-port direct conversion receiver for high-speed multi-band multi-mode wireless communication system such as software defined radio(SDR) is proposed. The designed receiver is composed of two CMOS four-port BPSK receivers and a dual-band one-stage polyphase filter for quadrature LO signal generation. The four-port BPSK receiver, implemented in 0.18 ${\mu}m$ CMOS technology for the first time in microwave-band, is composed of two active combiners, an active balun, two power detector, and an analog decoder. The proposed polyphase filter adopt type-I architecture, one-stage for reduction of the local oscillator power loss, and LC resonance structure instead of using capacitor for dual-band operation. In order to extent the operation RF bandwidth of the proposed six-port receiver, we include I/Q phase and amplitude calibration scheme in the six-port junction and the power detector. The calibration range of the phase and amplitude mismatch in the proposed calibration scheme is 8 degree and 14 dB, respectively. The validity of the designed six-port receiver is successfully demonstrated by modulating M-QAM, and M-PSK signal with 40 Msps in the two-band of 900 MHz and 2.4 GHz.

• The KIPS Transactions:PartC
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• v.14C no.3 s.113
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• pp.209-220
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• 2007

IPS(Intrusion Prevention Systems), which is installed in inline mode in a network, protects network from outside attacks by inspecting the incoming/outgoing packets and sessions, and dropping the packet or closing the sessions if an attack is detected in the packet. In the signature based filtering, the payload of a packet passing through IPS is matched with some attack patterns called signatures and dropped if matched. As the number of signatures increases, the time required for the pattern matching for a packet increases accordingly so that it becomes difficult to develop a high performance US working without packet delay. In this paper, we propose a high performance IPS based on signature hashing to make the pattern matching time independent of the number of signatures. We implemented the proposed scheme in a Linux kernel module in a PC and tested it using worm generator, packet generator and network performance measure instrument called smart bit. Experimental results show that the performance of existing method is degraded as the number of signatures increases whereas the performance of the proposed scheme is not degraded.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.374-387
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• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.12
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• pp.7287-7291
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• 2014

A CDTA (current differencing transconductance amplifier) is an active building block for current mode analog signal processing with the advantages of high linearity and a wide frequency bandwidth. In addition, it can generate a stable voltage because all the differencing input current flows to the grounded devices. In this paper, a new small signal equivalent circuit is proposed to analyze a CDTA. The proposed small signal equivalent circuit provides greater precision in analyzing the magnitude and frequency response than its previous counterparts because it considers the parasitic components of the input, internal and output terminal. In addition, observations of the changes made in various devices, such as the resistor (Rz) confirmed that those devices heavily influence the characteristics of CDTA. The designed parameters of the proposed small signal equivalent circuit of the CDTA provides convenience and accuracy in the further design of analog integrated circuits. For verification purposes, a 2.5 MHz low pass filter was designed on the HSPICE simulation program using the proposed small signal equivalent circuit of CDTA.

• The Transactions of the Korea Information Processing Society
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• v.3 no.2
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• pp.295-304
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• 1996

Toprovide economical BISDN service, with which integration process of many types of media is possible, it is necessary to construct a system with ground network and satellite network combined. The method for this type of transmission using satellite is TDMA that can provide services to many users in various area. However, the most difficult task to connect TDMA which uses synchronous method to ATM which used asynchronous transfer mode is the deterioration n of ATM transmission quality such as cell delay variation. Therefore, it is necessary to develop delay variation compensation method which can confront to the ATM. Efficient ways to use satellite links under the conditions such that maximum efficiency of the delay variation is limited under the required value, and the burst characteristic of transmission cell does not increase are being researched for translation between in ATM and TDMA. This paper points out the problems when time stamp method, reviewd in ground network, is applied to the satellite links to compensate the delay variation .To solve the problem, discrete cell count method is introduced along with the calculation of transmission capacity and error rate.Also, from the observation of stab-ility of the system and verification of reliability even when singal error occurred in the cell transmission timing information, the proposed compensation method appeared to be excellent.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11B
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• pp.920-929
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• 2004

Nowadays, wireless packet data services are provided over cdma2000 1x/1xEV-DO mobile communication network and Portable Internet are being standardized for users demanding higher data rate services. Portable Internet can provide high data rate services, but its service coverage is relatively small. If Portable Internet may be integrated with cdma2000 mobile networks, users are able to choose the best service according to service areas and get seamless services while they are moving around. At the same time, it is cost-effective for operators to construct and maintain the integrated network. For the purpose of effectively integrating Portable Internet into cdma2000 networks, we propose an integration scheme including network architecture, protocol architecture, functions in network elements, interfaces between them, and call-flow procedures. The integration scheme proposed in this paper adopts a tightly-coupled architecture for unified authentication/accounting and seamless services. In addition, the scheme can be implemented without modifying the existing cdma2000 mobile communication networks. It is also simple to develop the dual-mode mobile station. Through the simulation results based on the performance model for handoffs between cdma2000 and Portable Internet, it has teen validated that the proposed scheme diminishes packet losses compared with the loosely-coupled architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.702-709
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• 2003

In this paper, we propose an efficient and QoS-aware MAC scheduling algorithm for Bluetooth, which considers both throughput and delay performance of each Master-Slave pair in scheduling decisions, and thus, attempts to maximize overall performance. The proposed algorithm, MTDPP (Modified Throughput-Delay Priority Policy), makes up for the drawbacks of T-D PP (Throughput-Delay Priority Policy) proposed in [6] and improves the performance. Since Bluetooth employs a master-driven TDD based scheduling algorithm, which is basically operated with the Round Robin policy, many slots may be wasted by POLL or NULL packets when there is no data waiting for transmission in queues. To overcome this link wastage problem, several algorithms have been proposed. Among them, queue state-based priority policy and low power mode-based algorithm can perform with high throughput and reasonable fairness. However, their performances may depend on traffic characteristics, i.e., static or dynamic, and they require additional computational and signaling overheads. In order to tackle such problems, we propose a new scheduling algorithm. Performance of our proposed algorithm is evaluated with respect to throughput and delay. Simulation results show that overall performances can be improved by selecting suitable parameters of our algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.4
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• pp.582-593
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• 1999

This paper presents the design and fabrication of the diplexer for a KOREASAT-III Ka-band satellite transponder. The transmission characteristics of the diplexer is analyzed by calculating the generalized scattering matrix using mode matching method. It is composed of 2 bandpass filters, coupled with H-plane T-junction having symmetrical inductive iris and E-plane metal insert structures. Compared with the size and weight of the Rx and Tx filter loaded with a transponders respectively, those of the diplexer can be effectively reduced. In a high power transmission, the variation of the filter characteristics is minimized by the scheme that irises are extended to the exterior of H-plane of the waveguide. This scheme needs no extra heat sinks for dissipating high power. The diplexer is designed to improve the simplification, durability and reliability by eliminating tuning screws, which have been used to compensate for the characteristics of fabricated filters. The bandpass filters of the diplexer show the insertion loss of less than 1.2 dB and the return loss in excess of 15 dB. The isolations of more than 65 dB have been achieved between Rx and Tx filter.