• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.80-85
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• 2003

This paper proposes Galois Field Arithmetic Unit(GFAU) whose structure does addition, multiplication and division in GF(2m). GFAU can execute maximum two additions, or two multiplications, or one addition and one multiplication. The base architecture of this GFAU is a divider based on modified Euclid's algorithm. The divider was modified to enable multiplication and addition, and the modified divider with the control logic became GFAU. The GFAU for GF(2193) was implemented with Verilog HDL with top-down methodology, and it was improved and verified by a cycle-based simulator written in C-language. The verified model was synthesized with Samsung 0.35um, 3.3V CMOS standard cell library, and it operates at 104.7MHz in the worst case of 3.0V, 85$^{\circ}C$, and it has about 25,889 gates.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.253-256
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• 2001

G.UTE ADSL 모뎀에 적합한 주파수 영역 프로세서의 구조를 제안하였다. 주파수 영역의 연산과정에 대한 알고리듬 수준의 최적화를 수행하였고, 하드웨어 자원할당에 따른 설계의 효율성도 분석하였다. 제안된 프로세서는 한 개의 실수 곱셈기와 두 개의 실수 덧셈기를 병렬로 연결한 구조를 가지며, 기존의 연구결과에 비해 작은 하드웨어 크기를 차지한다. 설계된 시스템은 삼성 0.35㎛ 표준셀 라이브러리를 사용하여 합성하였으며, G.LITE ADSL 모뎀에 적합하게 적은 하드웨어 자원으로 필요한 연산을 효율적으로 수행한다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1997.10a
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• pp.402-408
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• 1997

일정 학습계수와 이진 강화함수를 지닌 자기조직화 형상지도(Self-Organizing Feature Map)신경회로망을 FPGA위에 하드웨어로 구현하였다. 원래의 SOFM 알고리즘에서 학습계수가 시간 종속형인데 반하여, 본 논문에서 하드웨어로 구현한 알고리즘에서는 학습계수가 일정인 값으로 고정되며 이로 인한 성능저하를 보상하기 위하여 이진 강화함수를 부가하였다. 제안한 알고리즘은 복잡한 곱셈 연산을 필요로 하지 않으므로 하드웨어 구현시 보다 쉽게 구현 가능한 특징이 있다. 1개의 덧셈/뺄셈기와 2개의 덧셈기로 구성된 단위 뉴런은 형대가 단순하면서 반복적이므로 하나의 FPGA위에서도 다수의 뉴런을 구현 할 수 있으며 비교적 소수의 제어 신호로서 이들을 모두 제어 가능할 수 있도록 설계하였다. 실험결과 각 구성부분은 모두 이상 없이 올바로 동작하였으며 각 부분이 모두 종합된 전체 시스템도 이상 없이 동작함을 알 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.

• Communications of Mathematical Education
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• v.19 no.3 s.23
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• pp.485-502
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• 2005

한 가지 문제에 대한 다양한 풀이 방법을 탐색하는 것은 수학적 대상의 성질을 발명, 일반화하는 것 뿐만 아니라, 학생들의 지적인 유창성 및 유연성 계발, 수학에 대한 심미적 가치의 함양을 위한 의미 있는 교수학적 경험을 제공할 수 있을 것이다. 본 연구에서는 고등학교 '미분과 적분'에 제시된 사인의 덧셈정리에 대한 다양한 증명 방법을 제시하고, 이를 분석하여 수학교수학적으로 의미로운 시사점을 도출하였다. 이를 통해, 사인의 덧셈정리에 대한 새로운 증명 방법의 탐색, 사인의 덧셈정리의 수학교수학적 활용의 다양한 가능성을 모색할 수 있는 기초자료를 제공할 것이며, 제시된 증명 방법들은 '미분과 적분'의 지도에서 심화학습 자료로도 활용할 수 있을 것이다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.35-44
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• 2002

In this paper, an implementation method of RSA exponentiator based on Radix-$2^k$ modular multiplication algorithm is presented and verified. We use Booth receding algorithm to implement Radix-$2^k$ modular multiplication and implement radix-16 modular multiplier using 2K-byte memory and CSA(carry-save adder) array - with two full adder and three half adder delays. For high speed final addition we use a reduced carry generation and propagation scheme called pseudo carry look-ahead adder. Furthermore, the optimum value of the radix is presented through the trade-off between the operating frequency and the throughput for given Silicon technology. We have verified 1,024-bit RSA processor using Altera FPGA EP2K1500E device and Samsung 0.3$\mu\textrm{m}$ technology. In case of the radix-16 modular multiplication algorithm, (n+4+1)/4 clock cycles are needed and the 1,024-bit modular exponentiation is performed in 5.38ms at 50MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1451-1459
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• 2004

In this paper, a low-power 32-point IMDCT structure is proposed for MP3. Through re-odering of IMDCT matrices, we propose the systolic structure operating with 16, 8, 4, 2, and 1 cycle, respectively. To reduce power consumption, multiplication of each sub blocks are implemented by add and shift operation with CSD(Canrmic sigled digit) form coefficients. To reduce, furthermore, the number of adders, we utilize the common sub-expression sharing techniques. With these techniques, the relative power consumption of the proposed structure is reduced by 58.4% comparison to the conventional structure using only 2's complement form coefficient. Validity of the proposed structure is proved through Verilog-HDL coding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2039-2044
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• 2008

The problem of an efficient hardware implementation of multiple constant multiplication is frequently encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements with respect to the area and power consumption. In this paper, we present an efficient specialized adder design method for two common subexpressions ($10{\bar{1}}$, 101) in canonic signed digit (CSD) coefficients. By Synopsys simulations of a radix-24 FFT example, it is shown that the proposed method leads to about 21%, 11% and 12% reduction in the area, propagation delay time and power consumption compared with the conventional methods, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.246-248
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• 2022

Binary Edwards curves (BEdC), a new form of elliptic curves proposed by Bernstein, satisfy the complete addition law without exceptions. This paper describes an efficient hardware implementation of point scalar multiplication on BEdC using projective coordinates. Modified Montgomery ladder algorithm was adopted for point scalar multiplication, and binary field arithmetic operations were implemented using 257-bit binary adder, 257-bit binary squarer, and 32-bit binary multiplier. The hardware operation of the BEdC crypto-core was verified using Zynq UltraScale+ MPSoC device. It takes 521,535 clock cycles to compute point scalar multiplication.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.12
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• pp.453-460
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• 2022

As high-performance quantum computers are expected to be developed, studies are being actively conducted to build a post-quantum security system that is safe from potential quantum computer attacks. When the Grover's algorithm, a representative quantum algorithm, is used to search for a secret key in a symmetric key cryptography, there may be a safety problem in that the security strength of the cipher is reduced to the square root. NIST presents the post-quantum security strength estimated based on the cost of the Grover's algorithm required for an attack of the cryptographic algorithm as a post-quantum security requirement for symmetric key cryptography. The estimated cost of Grover's algorithm for the attack of symmetric key cryptography is determined by the quantum circuit complexity of the corresponding encryption algorithm. In this paper, the quantum circuit of the SCHWAEMM algorithm, AEAD family of SPARKLE, which was a finalist in NIST's lightweight cryptography competition, is efficiently implemented, and the quantum cost to apply the Grover's algorithm is analyzed. At this time, the cost according to the CDKM ripple-carry adder and the unbounded Fan-Out adder is compared together. Finally, we evaluate the post-quantum security strength of the lightweight cryptography SPARKLE SCHWAEMM algorithm based on the analyzed cost and NIST's post-quantum security requirements. A quantum programming tool, ProjectQ, is used to implement the quantum circuit and analyze its cost.