• Journal of Korea Society of Industrial Information Systems
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• v.15 no.2
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• pp.1-9
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• 2010

Feistel and SPN are the two main structures in a block cipher. Feistel is a symmetric structure which has the same structure in encryption and decryption, but SPN is not a symmetric structure. In this paper, we propose a SPN which has a symmetric structure in encryption and decryption. The whole operations of proposed algorithm are composed of the even numbers of N rounds where the first half of them, 1 to N/2 round, applies a right function and the last half of them, (N+1)/2 to N round, employs an inverse function. And a symmetry layer is located in between the right function layer and the inverse function layer. In this paper, AES encryption and decryption function are selected for the right function and the inverse function, respectively. The symmetric layer is composed with simple matrix and round key addition. Due to the simplicity of the symmetric SPN structure in hardware implementation, the proposed modified AES is believed to construct a safe and efficient cipher in Smart Card and RFID environments where electronic chips are built in.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.3
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• pp.290-297
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• 2004

The control laws for cart-pole system are studied to see the schemes on which the control laws are made. Also, the odd symmetry of the relation between the output of the control laws and the system state vector is observed. Utilizing the symmetry in quantizing the system state variables and implementing the control laws into look-up table is discussed. Then, a CMAC is trained for a nonlinear control law for a cart-pole system such that the symmetry is conserved and its learning performance is evaluated. It is found that utilizing the symmetry is to reduce the memory requirement as well as the training period while improving the learning quality in terms of preserving the symmetry.

• Journal of KIISE:Software and Applications
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• v.31 no.5
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• pp.563-569
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• 2004

A set of Zernike moments has been successfully used for object recognition or content-based image retrieval systems. Real time applications using Zernike moments, however, have been limited due to its complicated definition. Conventional methods to compute Zernike moments fast have focused mainly on the radial components of the moments. In this paper, utilizing symmetric/anti-symmetric properties of Zernike basis functions, we propose a fast and efficient method for Zernike moments. By reducing the number of operations to one quarter of the conventional methods in the proposed method, the computation time to generate Zernike basis functions was reduced to about 20% compared with conventional methods. In addition, the amount of memory required for efficient computation of the moments is also reduced to a quarter. We also showed that the algorithm can be extended to compute the similar classes of rotational moments, such as pseudo-Zernike moments, and ART descriptors in same manner.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2939-2945
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• 2014

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.378-384
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• 2023

In this study, we aim to derive the descriptor vector conditions that can simultaneously achieve the efficiency and accuracy of artificial Neural Network Potentials (NNP). The material system selected is silicon, a highly applicable material in various industries. Atomic structure-dependent energy data for training artificial neural networks were generated through density functional theory calculations. Behler-Parrinello type atomic-centered symmetric functions were employed as descriptors, and various length vector NNPs were generated. These NNPs were applied to reproduce the structure and mechanical properties of silicon materials in molecular dynamics simulations. In our findings, the minimum vector length for achieving both learning and computational efficiency while maintaining property reproducibility is approximately 50. It was also observed that, for the same conditions, incorporating more angle-dependent symmetric functions into the descriptor vector, could enhance the accuracy of NNP. Our results can provide guidelines for optimizing the conditions of descriptor vectors to achieve both efficiency and accuracy of NNP, simultaneously.

• Review of KIISC
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• v.32 no.1
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• pp.57-63
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• 2022

공개키 암호에 치명적인 위협이 될 것으로 예상하는 양자 컴퓨터가 빠르게 발전하면서, 암호학계에서는 공개키 암호를 대체하기 위한 양자 내성 암호 개발이 주요 화두로 떠올랐다. 이와 더불어 양자 컴퓨팅 환경에서의 대칭키 암호 및 구조의 안전성에 관해서도 많은 연구가 제안됐다. 하지만, 해시함수에 대한 분석은 2020년 Hosoyamada와 Sasaki가 양자 컴퓨팅 환경에서 해시함수의 충돌쌍 공격을 제안하면서 비로소 연구자들의 관심을 받기 시작했다. 그들의 연구는 양자 컴퓨터를 이용할 수 있는 공격자가 고전 컴퓨터만을 이용할 수 있는 공격자보다 해시함수의 더 많은 라운드를 공격할 수 있음을 보여준다. 또한, 양자 컴퓨팅 환경에서 해시함수의 충돌쌍을 찾는 문제는 해시함수 자체의 안전성에도 영향이 있지만, 양자 내성 암호의 안전성에도 영향을 준다는 점에서 매우 중요하다. 본 논문에서는 해시함수 충돌쌍 공격이 수행되는 양자 환경과 기 제안된 양자 충돌쌍 공격을 제시한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.755-758
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• 2014

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend very differs with bottom gate voltage, channel length and thickness, and doping concentration.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10b
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• pp.434-436
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• 1999

MRI 촬상내의 체동에 의해 화상위에 나타나는 아티팩트를 제거하는 알고리즘에 관해서 기술한다. 종래의 반복적인 위상탐색법에 의한 제거법과는 달리, 위상 엔코딩 방향인 Y 방향의 체동에 대하여 MRI의 원리에 근거해서 체동과 화상의 위상공간에서의 대응관계를 해석해서 체동성분을 추출함으로써 아티팩트를 제거하는 새로운 알고리즘을 제안한다. 인체의 단층상에 있어서 피하지방 부위를 통과하는 Y방향의 한 라인상의 밀도분포는 대칭성을 갖고 있어 밀도분포위상의 선형성을 체동과 화상성분을 분리하기 위한 구속조건으로 사용한다. MRI 신호에 대해서 X 방향의 1차원 푸리에 변환을 행한 후의 Y 방향의 스펙트럼 위상값은 화상자신의 성분과 체동성분의 합이 되고 있다. Y 방향의 한 라인에 따른 밀도분포가 대칭인 경우에는 화상의 위상성분이 그 위치에 대해서 선형함수가 되고 있다. 이러한 구속조건에 근거한 아티팩트의 제거방법을 정식화하며, 시뮬레이션에 의해 본 방법의 유효성을 확인한다. 아울러, 체동 변동이 약간 큰 경우 및 Y 접선 영역의 대칭성이 무너진 경우에 대해서도 검토를 행한다.

• Electrical & Electronic Materials
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• v.9 no.3
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• pp.304-309
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• 1996

본 고에서는 초전도에 관한 학문적 연구내용의 추이와 그 응용기술의 개발내용을 간략히 살펴보았다. 고온 초전도의 형성원리에 대한 학문적 관심과 응용기술 개발사이의 괴리를 이해하려는 노력의 일환으로 고온 초전도체를 주대상으로 한 각종 연구결과들을 소개하면서 순수학문과 공학기술과의 긴밀한 연관성을 찾았다. 전자와 정공의 도핑 대칭성을 확립한 Nd-Ce-Cu-O의 발견은 물성의 정확한 이해에 기초한 성공이었고, 산화물 고온 초전도체들의 전자쌍 파동함수의 대칭성에 관한 논의들에서 최근 연구의 주종을 이루고 있는 Josephson-coupling과 Photoemission등의 직관적인 결과를 주는 측정 실험들은 고도의 첨단기술과 죠셉슨 접합 등의 새로운 초전도 물성개념의 정확한 이해를 요하는 연구들이었다. 이러한 새로운 초전도 개념들의 토대위에 현 응용분야들의 추세를 대략 살핌으로써 부실하나마 미래의 차원 높은 수요에 대비한 학문적, 기술적 준비를 시도해 보았다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.504-511
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• 2003

The property of circuit symmetry has long been applied to the Problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power minimization, utilizing circuit symmetries. First, we analyze and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose effective transformation algorithms to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.