• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Korean Institute of Traditional Landscape Architecture
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• v.31 no.2
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• pp.70-81
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• 2013

In this study, the locational and constructional characteristics of Jukrimseowon, pavilion Imrijeong, and Palgwaejeong located in Nonsan, Ganggyung-eup were reviewed and the interrelation of these three places were studied through references including records of those days; Sagyeyonbo(沙溪年譜), Jukrimseowon dorok(竹林書院都錄), Imrijeonggi(臨履亭記), Jukrimseowon Myojeongbi(竹林書院廟庭碑), Namyurok(南遊錄). The result is as follows. Jukrimseowon enshrining Yukhyeon(六賢) is arranged as 'Hongsalmoon-Woisalmoon-Dongjae(憲章堂; Heonjangdang)' and 'LIbrary-Naesammoon(神門; shin moon)-Sau(竹林祠: Jukimsa)', excluding a lecture hall. In case of Sagye Jangsang Kim's Imrijeong(沙溪金長生) and Uam Shiyoel Song(尤庵宋時烈)'s Palgwaejeong respectively constructed 50 meters and 10 meters each away from Jurimseowon, detail designs such as scale, roofs, surface, windows, doors, and tablets as well as its prospect are nearly identified. Especially Taking Imrijeong and Palgwaejeong's locational conditions composed of rocks centered on Jukrimseowon, those are maintain the bilateral symmetry as much as possible and surround the shrine. It appeared that the Jukrimseowon's shrine enshrining Yulgok(栗谷) and Ugye(牛溪) was rebuilt during the reconstruction of auditoriums because of political conditions after the renovation of Kiing Injo and it was called as 'Hwangsanseowon(黃山書院)' with Imrijeong which was a lecture hall. It was an inevitable consequence to keep the bilateral symmetry which is a basic order of auditorium structure by maintaining and using Imrijeong and Palgwaejeong as a lecture hall of the auditorium after the reconstruction at least. Consequently, the desperate attempt to adjust the arrangement and visual imbalance of Imrijeong built with periodical differences and Hwangsanseowon resulted from the construction of shrine was Palgwaejeong built under Monggoibyuk of Hwansan Taken these circumstances together, Jukrimseowon is a 'shrine-centered auditorium' with characteristics of auditorium, constructed by integrating Imrijeong which was used as a lecture hall after the construction of shrine and Palgwaejeong repaired through the reconstruction. The construction of Palgwaejeong and the formative conformity with Imrijeong are assumed as an consequence intended for the compensation of Jukrimseowon's function and role as an auditorium. This study will provide an opportunity to focus on the auditorium and pavilion's complementary function as well as the Confucian and constructional functions by revealing the fact that pavilions were established as a complementary facility for the lecture hall of auditorium.

• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.152-160
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• 2005

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. Conventional TSPC D-flip flops suffer from glitches, unbalanced propagation delay, and unnecessary charge/discharge at internal nodes in precharge phase, which results in increased power consumption. In this paper a new dynamic D-flip flop is proposed to overcome these problems. Glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The proposed D-flip flop is employed in designing a 128/129 dual-modulus prescaler using $0.18{\mu}m$ CMOS process parameters. The designed prescaler operates up to 5GHz while conventional one can operate up to 4.5GHz under same conditions. It consumes 0.394mW at 4GHz that is a 34% improved result compared with conventional one.

• Journal of the KSME
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• v.27 no.6
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• pp.504-514
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• 1987

복잡한 전자부품의 조립시에 필요한 열적 디자인에 관한 정보는 오래전부터 실험을 통하여 얻어지고 있다. 실험적 데이터를 이용하여 무차원 파라미터로 표시된 실험결과는 꼭 같지는 않지만 현상적으로는 비슷한 상황에 응용될 수 있다. 여기서는 학술문헌에 나타나 있는 자연대류에 관한 실험적인 상관관계식들과 프레임에 수직으로 꽂혀있는 균일가열 전자회로기판의 모델에서 얻어진 무차원 자료들을 비교하고자 한다. 대부분의 자료들은 수정채널 Rayleigh수(Ra")가 15~100범위에 속하며, 이러한 범위는 부품이 조밀하게 배치된 기관이 서로 좁은 채널을 이루고 있으며, 동시에 상당한 전력을 소비하고 있는 경우에 해당한다. Wirt와 Stutzman, Bar-Cohen과 Rohsenow의 일반상관관계식은 AT'||'&'||'T Bell 연구소에서 개발된 전자기기를 이용하여 수집한 실험데이터를 잘 표현하고 있으며 10 < Ra" <1,000범위에서 추천될 수 있다. 두개의 유사한 상관관계식과 비교할 때 상당히 좋은 예측을 보였으며 또한 Sparrow와 Gregg의 연구결과와도 잘 일치하므로 Ra" < 10인 경우에 Aung의 완전발달층류의 채널유동방식, Ra" > 1,000인 경우에는 Aung등의 단일 수직평판 근사식이 추천될 수 있다. Coyne의 알고리즘에 의한 계산치는 10

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1356-1366
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• 2011

The TPM(Trusted Platform Module) is a hardware chip to support a trusted computing environment. A rightful user needs a command authorization process in order to use principal TPM commands. To get command authorization from TPM chip, the user should perform the OIAP(Object-Independent Authorization Protocol) or OSAP(Object-Specific Authorization Protocol). Recently, Chen and Ryan alerted the vulnerability of insider attack on TPM command authorization protocol in multi-user environment and presented a countermeasure protocol SKAP(Session Key Authorization Protocol). In this paper, we simulated the possibility of insider attack on OSAP authorization protocol in real PC environment adopted a TPM chip. Furthermore, we proposed a novel countermeasure to defeat this insider attack and improve SKAP's disadvantages such as change of command suructures and need of symmetric key encryption algorithm. Our proposed protocol can prevent from insider attack by modifying of only OSAP command structure and adding of RSA encryption on user and decryption on TPM.

• The KIPS Transactions:PartC
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• v.14C no.6
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• pp.493-502
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• 2007

In this paper, we propose a handoff-aware DiffServ scheduler which intends to guarantee various QoS requirements of multimedia services for mobile nodes in TDD/CDMA based wireless networks. TDD is widely used duplexing mechanism in wireless communications. Unlike FDD, TDD allows a node to symmetrically communicate with a base station by using a single frequency band, resulting in high utilization of wireless resources. DiffServ is regarded as a relatively simple QoS support mechanism and thus it is easy to be extended. This is because DiffServ is not a per-flow based mechanisms and it does not require any signaling protocol. However, previously proposed DiffServ schedulers for wired networks can not be deployed directly into wireless networks since they do not consider properties of wireless networks. As a solution to the problem, DSS(DiffServ Supporting Scheduler) was proposed. DSS uses uplink channel, which is originally used for a node to require a base station to transmit packets, to support QoS efficiently. However, QoS does not consider handoff so that it can not support QoS for moving nodes from one cell to the other cell. Therefor. the proposed handoff support QoS mechanism is necessary for TCC/CDMA networks. The proposed scheme allows a mobile node to achieve seamless service without QoS degradation even for the handoff duration.

• Journal of the Korea Convergence Society
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• v.2 no.4
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• pp.29-37
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• 2011

Dispersed generation (DG) such as wind power (WP) and Photovoltaic systems (PV) that has been promoted at the national level recently is mainly being introduced into distribution systems adjacent to consumers because it is generation on a small scale when compared to current generation. Due to its characteristics, DG can be operated by interconnection with distribution systems to present security of more stable power and efficient use of power facilities and resources. Problems on protection coordination of distribution systems by reverse flow of DG can roughly be divided into three possibilities: excess in rated breaking capacity (12.5KA) of protective devices by a fault in DG current supply, failure to operate protective devices by an apparent effect that can occur by reduction in impedance parallel circuit fault current due to interconnection of DG, and malfunction of protective devices by interconnection transformer connection type. The purpose of this study is to analyze problems in protection coordination that can occur when DG is operated by interconnection with distribution systems by conducting modeling and simulations by using theoretical symmetrical components and MATLAB/SIMULINK to present methods to improve such problems.

• Journal of the Korean Society of Food Science and Nutrition
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• v.40 no.1
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• pp.63-69
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• 2011

To characterize the polysaccharides which exist as soluble forms in Korean traditional alcoholic beverages, the polysaccharides were isolated from Korean pear wine and their anti-complementary activities were examined. The main polysaccharide, PW-1 was purified to homogeneity from the crude polysaccharide (PW-0) in pear wine by size exclusion chromatography using Sephadex G-75. Molecular mass of PW-1 was estimated to be 150 kDa and it contained significant proportion of mannose (81.8%) and 5 different minor component sugars such as arabinose (1.2%), galactose (2.7%), glucose (8.5%), galacturonic acid (5.3%) and glucuronic acid (0.5%). These analyses indicated that the main polysaccharide in pear wine was mainly present as a mannan which had originated from the cell walls of fermenting yeasts. On the other hand, PW-1 showed potent anti-complementary activity in a dose-dependent fashion. Identification of C3 activation products by the crossed immunoelectrophoresis using anti-human C3 and anti-complementary activity of PW-1 in $Ca^{++}$-free condition suggested complement activations by PW-1 from Korean pear wine occur via both classical and alternative pathways.