• Title/Summary/Keyword: 대용량 메모리

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Development of Hypertext Encyclopedia (하이퍼텍스트 한글백과사전의 개발)

  • Jeon, Kyong-Hun;Kang, Hyun-Kyu;Kim, Young-Il;Park, Sang-Kyu;Choi, Key-Sun
    • Annual Conference on Human and Language Technology
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    • 1993.10a
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    • pp.59-70
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    • 1993
  • 개인용 컴퓨터가 많이 보급되고, CD-ROM과 같은 대용량의 기록장치가, 널리 퍼지면서, 전자화된 사전이 널리 사용되게 되었다. 그러나 이러한 전자사전들은 대개 매우 단순화된 탐색기능만을 제공하므로, 전자화의 잇점을 크게 살리지 못하고 있다. 따라서, 컴퓨터의 힘을 빌린, 보통의 종이로된 사전보다 훨씬 유용한 전자사전을 생각해 볼 수 있을 것이다. 이러한 노력이 과거 80년대 말에 하이퍼텍스트로 시작되어 이제는 매우 상업적인 곳에까지 사용되어지고있다. 국내에서도 전자사전의 개발은 다양하게 진행되어오고 있으나, 대부분 컴퓨터를 위한 사전, 다시 말하면, 빠른 접근시간, 적은 메모리사용만을 고려한 사전에 그치고 있다. 본 논문에서는 이러한 필요성에 부합하여, 백과사전자료를 가지고 사람을 위한 전자백과사전을 개발하는 방법을 소개한다. 특히, 이러한 개발과정을 자동화 할 수 있음을 보이고, 백과사전을 하이퍼텍스트로 자동변환하는 방법을 자세히 기술한다. 이 방법은 원시 자료를 하이퍼텍스트로 변환하기 좋은 정형화된 중간자료로 바꾸고, 이 중간자료와 기초적인 명사추출 알고리즘을 이용하여, 각 노드들 사이에 링크를 만드는 것이다. 또한, 이 방법을 이용하여 개발한 HE(Hypertext Encyclopedia) 시스템을 소개한다.

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Conceptual Design of High Speed Data Processing Unit for Next Generation Satellite (차세대 인공위성용 고속데이터 처리유닛 개념설계)

  • Oh, Dae-Soo;Seo, In-Ho;Lee, Jong-Ju;Park, Hong-Young;Chung, Tae-Jin;Kim, Hyung-Myung;Park, Jong-Oh;Yoon, Jong-Jin;Cha, Kyung-Hwan
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.36 no.6
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    • pp.616-620
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    • 2008
  • High reliability is the important parameter on designing satellite system and it is also important to design hish speed data processing unit. To make high speed satellite processing unit, it is needed to utilize space processor, high speed data interface technology, mass memory control technology and data protection technology under space radiation environment.

The Study on the Development of Historical Data Management System for Realtime EMS Data Storage & Retrieval (실시간 EMS데이터의 효율적인 저장 및 관리를 위한 이력데이터 관리 시스템 설계 및 구현)

  • Jang, Bok-Sun;Kim, Myoung-Ui;Kim, Wan-Hong;Yoon, Yeo-Jun
    • Proceedings of the Korean Information Science Society Conference
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    • 2007.10b
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    • pp.388-392
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    • 2007
  • 계속적으로 변화하는 방대한 양의 EMS 데이터를 실시간 취득하여, 사용자가 원하는 데이터만 추출해서 원하는 포맷으로 저장하여 추후 활용할 수 있는 HDMS 시스템에 대하여 소개한다. HDMS 시스템은 K-EMS 과제의 일부분으로 개발되었다. 공유메모리를 사용하여 데이터를 처리하는 실시간 DBMS로부터 추출된 대용량 데이터를 고속으로 디스크 DBMS로 입력하고, 데이터 손실에 대한 Risk를 감소시키기 위하여 동적인 파티션 추가삭제를 통하여 자동으로 분산저장하며, 자동 백업 기능을 제공하여 사용자의 편의성을 증진한다. 데이터를 장기간 보관하고, 보관된 데이터에 대한 데이터 검색 기능을 제공하기 위하여 백업과 관련된 메타데이터를 관리한다. 관리된 메타데이터를 이용하여 사용자의 요구에 의해 백업파일을 시스템에 자동으로 복구하여 온라인 보관주기가 경과한 데이터에 대해 조회가 가능하도록 한다. HDMS시스템은 CIM 기반으로 데이터베이스가 구축되어 향후 K-EMS 외의 타 시스템과의 데이터 통합 및 연계가 용이하고 여러 분야에서 데이터 재활용이 가능할 것으로 예상된다.

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Development and Test of KOMPSAT-2 MMD S/W (다목적실용위성 2호 대용량 메모리 및 지상송신관리 소프트웨어 개발 및 시험)

  • Chae, Dong-Seok;Lee, Jae-Seung;Choi, Jong-Wook;Kang, Soo-Yeon;Lee, Jong-In;Choi, Eun-Jung;Park, Suk-June
    • Proceedings of the Korea Information Processing Society Conference
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    • 2004.05a
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    • pp.1533-1536
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    • 2004
  • 위성의 비행소프트웨어는 위성이 주어진 임무를 수행할 수 있도록 위성을 제어하는 것으로 지상으로부터의 원격 명령을 받아 처리하고 원격측정 데이터를 지상으로 송신하는 기능과 자세 결정 및 제어, 전력 제어, 열 제어, 탑재체 관리 등의 기능을 수행한다. 본 논문은 다목적실용위성 2호의 비행소프트웨어에서 원격측정 데이터를 저장하고 지상으로 전송하는 기능을 수행하는 MMD (Mass Memory and Downlink Management) 소프트웨어의 설계 및 구현 내용과 시험절차, 방법, 시험결과 등에 대해서 서술하였다.

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Reliability Optimization Technique for High-Density 3D NAND Flash Memory Using Asymmetric BER Distribution (에러 분포의 비대칭성을 활용한 대용량 3D NAND 플래시 메모리의 신뢰성 최적화 기법)

  • Myungsuk Kim
    • IEMEK Journal of Embedded Systems and Applications
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    • v.18 no.1
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    • pp.31-40
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    • 2023
  • Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.

Design and Implementation of a Main-Memory Database System for Real-time Mobile GIS Application (실시간 모바일 GIS 응용 구축을 위한 주기억장치 데이터베이스 시스템 설계 및 구현)

  • Kang, Eun-Ho;Yun, Suk-Woo;Kim, Kyung-Chang
    • The KIPS Transactions:PartD
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    • v.11D no.1
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    • pp.11-22
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    • 2004
  • As random access memory chip gets cheaper, it becomes affordable to realize main memory-based database systems. Consequently, reducing cache misses emerges as the most important issue in current main memory databases, in which CPU speeds have been increasing at 60% per year, compared to the memory speeds at 10% per you. In this paper, we design and implement a main-memory database system for real-time mobile GIS. Our system is composed of 5 modules: the interface manager provides the interface for PDA users; the memory data manager controls spatial and non-spatial data in main-memory using virtual memory techniques; the query manager processes spatial and non-spatial query : the index manager manages the MR-tree index for spatial data and the T-tree index for non-spatial index : the GIS server interface provides the interface with disk-based GIS. The MR-tree proposed propagates node splits upward only if one of the internal nodes on the insertion path has empty space. Thus, the internal nodes of the MR-tree are almost 100% full. Our experimental study shows that the two-dimensional MR-tree performs search up to 2.4 times faster than the ordinary R-tree. To use virtual memory techniques, the memory data manager uses page tables for spatial data, non- spatial data, T-tree and MR-tree. And, it uses indirect addressing techniques for fast reloading from disk.

AFTL: An Efficient Adaptive Flash Translation Layer using Hot Data Identifier for NAND Flash Memory (AFTL: Hot Data 검출기를 이용한 적응형 플래시 전환 계층)

  • Yun, Hyun-Sik;Joo, Young-Do;Lee, Dong-Ho
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.1
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    • pp.18-29
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    • 2008
  • NAND Flash memory has been growing popular storage device for the last years because of its low power consumption, fast access speed, shock resistance and light weight properties. However, it has the distinct characteristics such as erase-before-write architecture, asymmetric read/write/erase speed, and the limitation on the number of erasure per block. Due to these limitations, various Flash Translation Layers (FTLs) have been proposed to effectively use NAND flash memory. The systems that adopted the conventional FTL may result in severe performance degradation by the hot data which are frequently requested data for overwrite in the same logical address. In this paper, we propose a novel FTL algorithm called Adaptive Flash Translation Layer (AFTL) which uses sector mapping method for hot data and log-based block mapping method for cold data. Our system removes the redundant write operations and the erase operations by the separating hot data from cold data. Moreover, the read performance is enhanced according to sector translation that tends to use a few read operations. A series of experiments was organized to inspect the performance of the proposed method, and they show very impressive results.

Improving Performance of File-referring Octree Based on Point Reallocation of Point Cloud File (포인트 클라우드 파일의 측점 재배치를 통한 파일 참조 옥트리의 성능 향상)

  • Han, Soohee
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.33 no.5
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    • pp.437-442
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    • 2015
  • Recently, the size of point cloud is increasing rapidly with the high advancement of 3D terrestrial laser scanners. The study aimed for improving a file-referring octree, introduced in the preceding study, which had been intended to generate an octree and to query points from a large point cloud, gathered by 3D terrestrial laser scanners. To the end, every leaf node of the octree was designed to store only one file-pointer of its first point. Also, the point cloud file was re-constructed to store points sequentially, which belongs to a same leaf node. An octree was generated from a point cloud, composed of about 300 million points, while time was measured during querying proximate points within a given distance with series of points. Consequently, the present method performed better than the preceding one from every aspect of generating, storing and restoring octree, so as querying points and memorizing usage. In fact, the query speed increased by 2 times, and the memory efficiency by 4 times. Therefore, this method has explicitly improved from the preceding one. It also can be concluded in that an octree can be generated, as points can be queried from a huge point cloud, of which larger than the main memory.

A Buffer Architecture based on Dynamic Mapping table for Write Performance of Solid State Disk (동적 사상 테이블 기반의 버퍼구조를 통한 Solid State Disk의 쓰기 성능 향상)

  • Cho, In-Pyo;Ko, So-Hyang;Yang, Hoon-Mo;Park, Gi-Ho;Kim, Shin-Dug
    • The KIPS Transactions:PartA
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    • v.18A no.4
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    • pp.135-142
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    • 2011
  • This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

Design of a Large-density MTP IP (대용량 MTP IP 설계)

  • Kim, YoungHee;Ha, Yoon-Kyu;Jin, Hongzhou;Kim, SuJin;Kim, SeungGuk;Jung, InChul;Ha, PanBong;Park, Seungyeop
    • Journal of IKEEE
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    • v.24 no.1
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    • pp.161-169
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    • 2020
  • In order to reduce the manufacturing cost of MCU chips used in applications such as wireless chargers and USB-C, compared to DP-EEPROM (Double Poly EEPROM), which requires 3 to 5 additional process masks, it is even more necessary MTP(Multi-Time Programmable), which is less than one additional mask and have smaller unit cell size. In addition, in order to improve endurance characteristics and data retention characteristics of the MTP memory cell due to E/P(Erase / Program) cycling, the distribution of the VTP(Program Threshold Voltage) and the VTE(Erase Threshold Voltage) needs to be narrow. In this paper, we proposed a current-type BL S/A(Bit-Line Sense Amplifier) circuit, WM(Write Mask) circuit, BLD(BL Driver) circuit and a algorithm, which can reduce the distribution of program and VT and erase VT, through compare the target current by performing the erase and program pulse of the short pulse several times, and if the current specification is satisfied, the program or erase operation is no longer performed. It was confirmed that the 256Kb MTP memory fabricated in the Magnachip semiconductor 0.13㎛ process operates well on the wafer in accordance with the operation mode.