• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.2
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• pp.157-167
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• 2003

In this paper, to reduce the resonant length of patch, microstrip patch antenna of linear polarization which is suppressed at two radiation edges is designed and fabricated at the frequency of 1.575 GHz. The result is like that the resonant length of patch is 45 mm and the length reduction effect is 43.8 % when it is compared with that(80 mm) of plane type. The gain is 4.4 dBd and -3 dB beamwidths are 112$^{\circ}$ and 66$^{\circ}$ in the E-plane and H-plane, respectively. Also, to reduce the size of patch, microstrip patch antennas those are suppressed at four radiating comers are designed and fabricated at the same frequency in the linear and circular polarization, respectively. For linear polarization, at the 1.2 of width/length(W/L) ratio, the patch area is 53 mm $\times$ 63.6 mm and the size reduction effect is 56.1 % when compared with that(80 mm $\times$ 96 mm) of plane type. The gain is 4.3 dBd and the -3 dB beamwidths are 120$^{\circ}$ and 78$^{\circ}$ in the E-plane and H-plane, respectively. For circular polarization, the patch size(54.2 mm $\times$ 61.5 mm) is reduced by 47.2 % than that(76 mm $\times$ 83 mm) of plane type. -3 dB beamwidth of horizontal polarization in the z-x plane and vortical polarization in the y-z plane are 108$^{\circ}$ and 93$^{\circ}$, respectively and this means the increasement in both planes by 52$^{\circ}$ and 27$^{\circ}$ than those of plane type. The maximum gain is 2.5 dBd in the horizontal polarization in the z-x plane. Axial ratio is 1.5 dB at 1.575 GHz and the 2 dB axial ratio bandwidth(ARBW) is 20 MHz(1.3 %).

• Geophysics and Geophysical Exploration
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• v.14 no.1
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• pp.98-104
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• 2011

Numerical simulation in exploration geophysics provides important insights into subsurface wave propagation phenomena. Although elastic wave simulations take longer to compute than acoustic simulations, an elastic simulator can construct more realistic wavefields including shear components. Therefore, it is suitable for exploration of the responses of elastic bodies. To overcome the long duration of the calculations, we use a Graphic Processing Unit (GPU) to accelerate the elastic wave simulation. Because a GPU has many processors and a wide memory bandwidth, we can use it in a parallelised computing architecture. The GPU board used in this study is an NVIDIA Tesla C1060, which has 240 processors and a 102 GB/s memory bandwidth. Despite the availability of a parallel computing architecture (CUDA), developed by NVIDIA, we must optimise the usage of the different types of memory on the GPU device, and the sequence of calculations, to obtain a significant speedup of the computation. In this study, we simulate two- (2D) and threedimensional (3D) elastic wave propagation using the Finite-Difference Time-Domain (FDTD) method on GPUs. In the wave propagation simulation, we adopt the staggered-grid method, which is one of the conventional FD schemes, since this method can achieve sufficient accuracy for use in numerical modelling in geophysics. Our simulator optimises the usage of memory on the GPU device to reduce data access times, and uses faster memory as much as possible. This is a key factor in GPU computing. By using one GPU device and optimising its memory usage, we improved the computation time by more than 14 times in the 2D simulation, and over six times in the 3D simulation, compared with one CPU. Furthermore, by using three GPUs, we succeeded in accelerating the 3D simulation 10 times.

• Journal of KIISE:Information Networking
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• v.35 no.2
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• pp.99-111
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• 2008

In recent years, the needs for WLANs(Wireless Local Area Networks) technology which can access to Internet anywhere have been dramatically increased particularly in SOHO(Small Office Home Office) and Hot Spot. However, unlike wired networks, there are some unique characteristics of wireless networks. These characteristics include the burst packet losses due to unreliable wireless channel. Note that burst packet losses, which occur when the distance between the wireless station and the AP(Access Point) increase or when obstacles move temporarily between the station and AP, are very frequent in 802.11 networks. Conversely, due to burst packet losses, the performance of 802.11 networks are not always as sufficient as the current application require, particularly when they use TCP at the transport layer. The high packet loss rate over wireless links can trigger unnecessary execution of TCP congestion control algorithm, resulting in performance degradation. In order to overcome the limitations of WLANs environment, MAC-layer LDA(Loss Differentiation Algorithm)has been proposed. MAC-layer LDA prevents TCP's timeout by increasing CRD(Consecutive Retry Duration) higher than burst packet loss duration. However, in the wireless channel with high packet loss rate, MAC-layer LDA does not work well because of two reason: (a) If the CRD is lower than burst packet loss duration due to the limited increase of retry limit, end-to-end performance is degraded. (b) energy of mobile device and bandwidth utilization in the wireless link are wasted unnecessarily by Reducing the drainage speed of the network buffer due to the increase of CRD. In this paper, we propose a new retransmission module based on Cross-layer approach, called BLD(Burst Loss Detection) module, to solve the limitation of previous link layer retransmission schemes. BLD module's algorithm is retransmission mechanism at IEEE 802.11 networks and performs retransmission based on the interaction between retransmission mechanisms of the MAC layer and TCP. From the simulation by using ns-2(Network Simulator), we could see more improved TCP throughput and energy efficiency with the proposed scheme than previous mechanisms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11B
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• pp.980-990
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• 2004

In this paper, we propose the dynamic bandwidth allocation algorithm for the IEEE802.3ah Ethernet Passive Optical Network(EPON) system to provide the fairness among terminals, and evaluate the delay-throughput performance by simulation. For the conventional EPON systems, an Optical Line Termination (OLT) schedules the upstream bandwidth for each Optical Network Unit (ONU), based on its buffer state. This scheme can provide a fair bandwidth allocation for each ONU. However, it has a critical problem that it does not guarantee the fair bandwidth among terminals which are connected to ONUs. For an example, we assume that the traffic from a greedy terminal increases at a time. Then, the buffer state of its ONU is instantly reported to the OLT, and finally the OW can get more bandwidth. As a result, the less bandwidth is allocated to the other ONUs, and thus the transfer delay of terminals connected to the ONUs gets inevitably increased. Noting that this unfairness problem exists in the conventional EPON systems, we propose a fair bandwidth allocation scheme by OLT with considering the buffer state of ONU as welt as the number of terminals connected it. For the performance evaluation, we develop the EPON simulation model with SIMULA simulation language. From the result of the throughput-delay performance and the dynamics of buffer state along time for each terminal and ONU, respectively, one can see that the proposed scheme can provide the fairness among not ONUs but terminals. Finally, it is worthwhile to note that the proposed scheme for the public EPON systems might be an attractive solution for providing the fairness among subscriber terminals.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.664-672
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• 2004

Widespread popularity of wireless data communication devices, coupled with the availability of higher bandwidths, has led to an increased user demand for content-rich media such as images and videos. Since such content often tends to be private, sensitive, or paid for, there exists a requirement for securing such communication. However, solutions that rely only on traditional compute-intensive security mechanisms are unsuitable for resource-constrained wireless and embedded devices. In this paper, we propose a selective partial image encryption scheme for image data hiding , which enables highly efficient secure communication of image data to and from resource constrained wireless devices. The encryption scheme is invoked during the image compression process, with the encryption being performed between the quantizer and the entropy coder stages. Three data selection schemes are proposed： subband selection, data bit selection and random selection. We show that these schemes make secure communication of images feasible for constrained embed-ded devices. In addition we demonstrate how these schemes can be dynamically configured to trade-off the amount of ded devices. In addition we demonstrate how these schemes can be dynamically configured to trade-off the amount of data hiding achieved with the computation requirements imposed on the wireless devices. Experiments conducted on over 500 test images reveal that, by using our techniques, the fraction of data to be encrypted with our scheme varies between 0.0244％ and 0.39％ of the original image size. The peak signal to noise ratios (PSNR) of the encrypted image were observed to vary between about 9.5㏈ to 7.5㏈. In addition, visual test indicate that our schemes are capable of providing a high degree of data hiding with much lower computational costs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1173-1183
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• 2006

In this paper, we propose an efficient method for improving visual quality of AR-FGS (Adaptive Reference FGS) which is adopted as a key scheme for SVC (Scalable Video Coding) or H.264 scalable extension. The standard FGS (Fine Granularity Scalability) adopts AR-FGS that introduces temporal prediction into FGS layer by using a high quality reference signal which is constructed by the weighted average between the base layer reconstructed imageand enhancement reference to improve the coding efficiency in the FGS layer. However, when the enhancement stream is truncated at certain bitstream position in transmission, the rest of the data of the FGS layer will not be available at the FGS decoder. Thus the most noticeable problem of using the enhancement layer in prediction is the degraded visual quality caused by drifting because of the mismatch between the reference frame used by the FGS encoder and that by the decoder. To solve this problem, we exploit the principle of cyclical block coding that is used to encode quantized transform coefficients in a cyclical manner in the FGS layer. Encoding block coefficients in a cyclical manner places 'higher-value' bits earlier in the bitstream. The quantized transform coefficients included in the ealry coding cycle of cyclical block coding have higher probability to be correctly received and decoded than the others included in the later cycle of the cyclical block coding. Therefore, we can minimize visual quality degradation caused by bitstream truncation by adjusting weighting factor to control the contribution of the bitstream produced in each coding cycle of cyclical block coding when constructing the enhancement layer reference frame. It is shown by simulations that the improved AR-FGS scheme outperforms the standard AR-FGS by about 1 dB in maximum in the reconstructed visual quality.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.7
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• pp.711-719
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• 2011

A study of miniaturization of an L-band orthomode transducer(OMT) for field experiments of radar backscatter is presented in this paper. The proposed OMT is not required the additional waveguide taper structures to connect with a standard adaptor by the newly designed junction structure which bases on a waveguide taper. Total length of the OMT for L-band is about 1.2 ${\lambda}_o$(310 mm) and it's a size of 60 % of the existing OMTs. And, to increase the matching and isolation performances of each polarization, two conducting posts are inserted. The bandwidth of 420 MHz and the isolation level of about 40 dB are measured in the operating frequency. The L-band scatterometer consisting of the manufactured OMT, a horn-antenna and network analyzer(Agilent 8753E) was used STCT and 2DTST to analysis the measurement accuracy of radar backscatter. The full-polarimetric RCSs of test-target, 55 cm trihedral corner reflector, measured by the calibrated scatterometer have errors of -0.2 dB and 0.25 dB for vv-/hh-polarization, respectively. The effective isolation level is about 35.8 dB in the operating frequency. Then, the horn-antenna used to measure has the length of 300 mm, the aperture size of $450{\times}450\;mm^2$, and HPBWs of $29.5^{\circ}$ and $36.5^{\circ}$ on the principle E-/H-planes.