• Title/Summary/Keyword: 단열회로

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A Study of an 8-b*8-b adiabatic pipelined multiplier with simplified supply clock generator (단열 회로를 이용한 8-b*8-b 파이프라인 승산기와 개선된 전원 클럭 발생기의 연구)

  • Mun, Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.4
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    • pp.43-43
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    • 2001
  • 단열회로를 이용한 8-b×8-b 파이프라인 승산기와 4가지 위상을 가지는 전원클럭을 공급하기 위한 개선 된 구조의 전원클럭 발생기를 설계하였다. 전원클럭 신호선의 전하는 복원되어 에너지 소모를 줄인다. 단열회로는 ECRL 형태를 기본으로 하였으며 0.6㎛ CMOS 공정을 사용하여 설계하였다. 개선된 전원클럭 발생기는 기존회로보다 4∼11% 정도 효율이 높았다. 모의실험결과 제안하는 단열회로 승산기는 CMOS 승산기보다 2.6∼3.5배 정도의 에너지를 감소시켰다.

A Design of 16-bit Adiabatic Low-Power Microprocessor (단열회로를 이용한 16-bit 저전력 마이크로프로세서의 설계)

  • Shin, Young-Joon;Lee, Byung-Hoon;Lee, Chan-Ho;Moon, Yong
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.6
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    • pp.31-38
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    • 2003
  • A 16-bit adiabatic low-power Microprocessor is designed. The processor consists of control block, multi-port register file, program counter, and ALU. An efficient four-phase clock generator is also designed to provide power clocks for adiabatic processor. Adiabatic circuits based on efficient charge recovery logic(ECRL), are designed 0.35,${\mu}{\textrm}{m}$ CMOS technology. Conventional CMOS processor is also designed to compare the energy consumption of microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is reduced by a factor of 2.9∼3.1 compared to that of conventional CMOS microprocessor.

A Study of an 8-b${\times}$8-b Adiabatic Pipelined Multiplier with Simplified Supply Clock Generator (단열회로를 이용한 8-b${\times}$8-b 파이프라인 승산기와 개선된 전원클럭 발생기의 연구)

  • Moon, Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.4
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    • pp.285-291
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    • 2001
  • An 8-b$\times$8-b adiabatic pipelined multiplier is designed. Simplified four phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and are integrated using 0.6${\mu}{\textrm}{m}$ CMOS technology. The efficiency of proposed supply clock generator is better than the previous one by 4~11%. Simulation results show that the power consumption of adiabatic pipelined multiplier is reduced by a factor of 2.6~3.5 compared to a conventional pipelined CMOS multiplier.

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Energy-saving Design Eased on Latched Pass-transistor Adiabatic Logic (래치형 패스 트랜지스터 단열 논리에 기반을 둔 에너지 절약 회로의 설계)

  • 박준영;홍성제;김종
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.10a
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    • pp.556-558
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    • 2004
  • 최근 VLSI 설계 분야에서, 단열 논리는 에너지 효율성이 뛰어난 저전력 설계 기술 중 하나로 각광 받고 있다. 이러한 단열 논리는 기존의 저전력 회로 설계를 위해 사용되었던 CMOS 논리들을 서서히 대체해 나갈 컷으로 기대되고 있다. 하지만 않은 단열 논리들의 제시에도 불구하고, 기존의 CMOS논리들을 단열 논리로 대체하는 기법에 관한 연구는 거의 없는 실정이다. 이 논문에서는 래치형 패스 트랜지스터 단열 논리(LPAL)와 이를 이용한 저전력 설계 기법을 소개하였다. 래치형 패스 트랜지스터 단열 논리는 기존의 단열 논리들이 가지고 있는 단정을 해결하고, 보다 저전력 지향적으로 CMOS논리를 대체 할 수 있다는 장점을 가진다.

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외단열 건물의 열부하계산법

  • 조민관
    • The Magazine of the Society of Air-Conditioning and Refrigerating Engineers of Korea
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    • v.32 no.2
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    • pp.28-39
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    • 2003
  • 1998년 4월 일본 공기조화.위생공학회 북해도지부 설비기술연구회에서는 실무레벨의 "외단열건물의 열부하계산법"을 위한 소위원회가 발족되었으며, 1999년 11월에 연구보고서가 완성되었다. 이에, 일본 학회에서는 건축설비기술자협회 북해도 지부와 공동으로 실무자를 대상으로 세미나를 2000년8월에 개최하였다. 본 내용은 위원회보고서와 세미나에 서 거론된 "외단열건물의 열부하특성과 계산법의 요점"을 제시하고 이에 근거한 최대부하의 합리적인 설계와 불가분의 관계가 있는 "외단열건물을 위한 난방과 냉방을 통일한 열부하계산법의 개념"을 소개함과 동시에 "실무자의 과제와 금후의 전망"에 대하여 언급하고자 한다.

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Geometric and Kinematic Characteristics of Fracture System in the Sancheong Anorthosite Complex, Korea (산청 회장암복합체 내 발달하는 단열계의 기하학적·운동학적 특성)

  • Lee, Deok-Seon;Kang, Ji-Hoon
    • The Journal of the Petrological Society of Korea
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    • v.25 no.4
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    • pp.389-400
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    • 2016
  • The study area, which is located in the southeastern part of the Jirisan province of the Yeongnam massif, Korea, consists mainly of the Precambrian Sancheong anorthosite complex and the Jirisan metamorphic rock complex, the Mesozoic granitoids which intruded them. Several fracture sets with various geometric indicators, which determine their relative timing and shear sense, are well observed in the Sancheong anorthosite complex. The aim of this study is to determine the development sequence of extension fractures, the movement sense and development sequence of shear fractures in the Sancheong anorthosite complex on the basis of detailed analysis of their geometric indicators. This study suggests fracture system of the Sancheong anorthosite complex was formed at least through five different fracturing events, named as Dn to Post-Dn+3 phases. (1) Dn phase: extension fracturing event of NNW trend. The fracture set experienced the reactivations of dextral ${\rightarrow}$ sinistral shearing with the change of stress field afterward. (2) Dn+1 phase: extension fracturing event of (N)NE trend. The fracture set experienced the reactivations of sinistral ${\rightarrow}$ sinistral ${\rightarrow}$ dextral. (3) Dn+2 phase: extension fracturing event of NW trend. The fracture set experienced the activated of dextral shearing. (4) Dn+3 phase: extension fracturing event of N-S trend. (5) Post-Dn+3 phase: extension fracturing event of (E)NE trend. Dn deformation formed during the early Songnim orogeny. Dn+1 deformation formed during the late Songnim orogeny. Dn+2 deformation formed during the Daebo orogeny. Dn+3 deformation formed during the Bulguksa orogeny.

A Design and Implementation of 16-bit Adiabatic ALU for Micro-Power Processor (초저전력 프로세서용 16-bit 단열 ALU의 설계 및 구현)

  • Lee, Han-Seung;Na, In-Ho;Moon, Yong;Lee, Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.3
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    • pp.101-108
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    • 2004
  • A 16-bit adiabatic ALU(arithmetic logic unit) is designed. A simplified four-phase clock generator is also designed to provide supply clocks for the adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on ECRL (efficient charge recovery logic) using a 0.35${\mu}{\textrm}{m}$ CMOS technology. The post-layout simulation results show that the power consumption of the adiabatic ALU including supply clock generator is reduced by a factor of 1.15-1.77 compared to the conventional CMOS ALU with the same structure.

Study on Low Power LED Display Operation (LED 디스플레이의 저전력화 동작 연구)

  • Lee, Kyung-Ryang;Kim, Jong-Un;Yeo, Sung-Dae;Cho, Seung-Il;Kim, Seong-Kweon
    • The Journal of the Korea institute of electronic communication sciences
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    • v.10 no.5
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    • pp.587-592
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    • 2015
  • According to increase in the use of the LED, the demand for low power consumption LED display design of the controller block has increased. In this paper, the low power LED controller block was designed through the power source supply that leads adiabatic operation from constant current source circuit operated by digital signal control. The proposed circuit was implemented using a 0.35um CMOS process. and it demonstrated linear operation of the circuit. From the simulation result, the proposed circuit was evaluated with about 82% power consumption reduction effect in comparison with conventional LED controller block. This research is expected to be helpful for the low power operation and the solution for heat problem of LED display.

A Study on the Energy Consumption Cost in the Winter and Calorific Value by Insulated Gang-form (단열갱폼 적용에 따른 동절기 보양비 사용량 및 발열량 검토에 관한 실험적 연구)

  • Nam, Kyung-Yong;Choi, Suk;Ahn, Sung-Jin;Lim, Myung-Kwan
    • Journal of the Korea Institute of Building Construction
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    • v.20 no.1
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    • pp.53-60
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    • 2020
  • This paper aims to examine the insulation performance of insulated gang form by changing the energy (power) consumption and concrete calorific value to assist in concrete protection in cold weather. According to the test results, the general gang form will generate three times the energy (power) consumption for 12 hours after the concrete is poured. In contrast, insulated gang foam consumed no energy (power) for 21 hours after pouring. The final power consumption was 3.7 times higher than that of the general gang form, confirming the improved performance of insulated gang form with regard to energy (power) consumption. The calorific value examination shows that the calorific value changes significantly according to the change of outside temperature after concrete placement in the case of the general gang form. However, in the case of the insulated gang form, only a slight heat loss occurred in the part of the frame, and it showed a constant heating pattern from the concrete casting to the demolding of the mold.

Geometrical Interpretation on the Development Sequence and the Movement Sense of Fractures in the Cheongsong Granite, Gilan-myeon Area, Uiseong Block of Gyeongsang Basin, Korea (경상분지 의성지괴 길안면지역에서 청송화강암의 단열 발달사 및 운동성에 대한 기하학적 해석)

  • Kang, Ji-Hoon;Ryoo, Chung-Ryul
    • The Journal of the Petrological Society of Korea
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    • v.15 no.4 s.46
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    • pp.180-193
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    • 2006
  • The Gilan area in the central-northern part of Uiseong Block of Cretaceous Gyeongsang Basin is composed of Precambrian metamorphic rocks, Triassic Cheongsong granite, Early Cretaceous Hayans Group, and Late Cretaceous-Paleocene igneous rocks. In this area, the faults of various directions are developed: Oksan fault of $NS{\sim}NNW$ trend, Gilan fault of NW trend, Hwanghaksan fault of WNW trend, and Imbongsan fault of EW trend. Several fracture sets with various geometric indicators, which determine their relative timing (sequence and coexistence relationships) and shear sense, we well observed in the Cheongsong granite, the basement of Gyeongsang Basin. The aim of this study is to determine the development sequence of extension fractures and the movement sense of shear fractures in the Gitan area on the basis of detailed analysis of their geometric indicators (connection, termination, intersection patterns, and cross-cutting relations). This study suggests that the fracture system of the Gilan area was formed at least through seven different fracturing events, named as Pre-Dn to Dn +5 phases. The orientations of fracture sets show (W) NW, NNW, NNE, EW, NE in descending order of frequency. The orientation and frequency patterns are concordant with those of faults around and in the Gilan area on a geological map scale. The development sequence and movement sense of fracture sets are summarized as follows. (1) Pre-Dn phase: extension fracturing event of $NS{\sim}NNW$ and/or $WNW{\sim}ENE$ trend. The joint sets of $NS{\sim}NNW$ trend and of $WNW{\sim}ENE$ trend underwent the reactivation histories of sinistral ${\rightarrow}$dextral${\rightarrow}$sinistral shearing and of (dextral${\rightarrow}$) sinistral shearing with the change of stress field afterward, respectively. (2) Dn phase: that of NW trend. The joint set experienced the reactivations of sinistral${\rightarrow}$dextral shearing. (3) Dn + 1 phase: that of $NNE{\sim}NE$ trend. The joint set was reactivated as a sinistral shear fracture afterward. (4) Dn +2 phase: that of $ENE{\sim}EW$ trend. (5) Dn +3 phase: that of $WNW{\sim}NW$ trend. (6) Dn+4 phase: that of NNW trend. The joint set underwent a dextral shearing after this. (7) The last Dn +5 phase: that of NNE trend.