• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.305-310
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• 2013

In this paper, the pressure sensor usable in a high temperature, using a SDB(silicon-direct-bonding) wafer of Si/$SiO_2$/Si-sub structure was provided and studied the characteristic thereof. The pressure sensor produces a piezoresistor by using a single crystal silicon as a first layer of SDB wafer, to thus provide a prominent sensitivity, and dielectrically isolates the piezoresistor from a silicon substrate by using a silicon dioxide layer as a second layer thereof, to be thus usable even under the high temperature over $120^{\circ}C$ as a limited temperature of a general silicon sensor. The measured result for a pressure sensitivity of the pressure sensor has a characteristic of high sensitivity, and its tested result for an output of the sensor further has a very prominent linearity and hysteresis characteristic.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.3 s.94
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• pp.253-259
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• 2005

In this paper, BaSrTiO$_{3}$(BST) thin film tunable interdigital capacitor using low cost silicon substrate instead of expensive single-crystalline substrate is presented. The tunable capacitor in which BST thin film is deposited by PLD has operation frequency and applied bias up to 4 GHz and 50 V, respectively. The maximum tunability in capacitance is found to be 30$\%$, for an applied field of 5 kV/cm at a bias of 50 V. Therefore, it has been shown that the BST microwave tunable capacitor can be integrated onto Si substrate.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.376-377
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• 2011

결정질 실리콘 태양전지 연구에 있어서 가장 중요한 부분은 재료의 저가화와 공정의 단순화에 의한 저가의 태양전지 셀 제작 부분과 고효율의 태양전지 셀 제작 부분이다. 본 논문에서는 마이크로 블라스터를 이용하여 폐 실리콘 웨이퍼를 태양전지용 재생웨이퍼를 제작함으로써 고효율을 가지는 단결정 실리콘 웨이퍼를 저 가격에 생산하기 위한 것이다. 특히 마이크로 블라스터를 이용하여 폐 실리콘 웨이퍼를 가공 할 때 표면에 생성되는 요철은 기존 태양전지 셀 제작에서 텍스쳐링 공정과 같은 표면 구조를 가지게 됨으로써 태양전지 셀에 제작 공정을 줄일 수 있는 효과도 가지게 된다. 마이크로 블라스터는 챔버 내에 압축된 공기나 가스에 의해 가속 된 미세 파우더들이 재료와 충돌하면서 재료에 충격을 주고 그 충격에 의해 물질이 식각되는 기계적 건식 식각 공정 기술이다. 이러한 물리적 충격을 이용하는 마이크로 블라스터 공정은 기존 재생웨이퍼 제작 공정 보다 낮은 재처리 비용으로 간단하게 태양전지용 재생웨이퍼를 제작 할 수 있다. 하지만 마이크로 블라스터를 이용하면 표면에 식각된 미세 파티클의 재흡착이 일어나게 되므로 이를 제거하기 위하여 DRE(damage remove etching) 공정이 필요하게 된다. 본 연구에서는 이방성, 등방성 식각 공정으로 태양전지용 재생웨이퍼를 제작하기 위해 가장 적합한 DRE 공정을 찾기 위해 등방성 식각은 RIE 식각으로, 그리고 이방성 식각은 TMAH 식각을 이용하였다. 마이크로 블라스터 공정 후 표면 반사율과 SEM 사진을 이용한 표면 요철 구조를 확인 하였고, DRE 공정 후 표면 반사율과 SEM 사진을 이용하여 표면 요철 구조를 확인 하였다. 각각의 lifetime을 측정하여 표면 식각으로 생성된 결함들을 분석하여 태양전지용 재생웨이퍼 제작에 가장 적합한 공정을 확인 하였다.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.149-154
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• 2005

We fabricated Ni/Co(or Co/Ni) composite silicide layers on the non-patterned wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\~}1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the poly silicon inversion due to fast metal diffusion lead to decrease silicide thickness. Our results imply that we should consider the serious inversion and fast transformation in designing and process f3r the nano-height fully cobalt nickel composite silicide gates.

• Journal of Radiation Protection and Research
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• v.40 no.2
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• pp.73-78
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• 2015

In this study, a scintillation detector was fabricated using a silicon photomultiplier (SiPM) and a Ce:GAGG scintillator single crystal, and its spectroscopic properties were compared with those of commercially available LYSO and CsI:Tl scintillators using ${\gamma}$-ray spectroscopy. The energy resolutions of the self-produced scintillation detector composed of the scintillator single crystal (volume: $3{\times}3{\times}20mm^3$) and SiPM (Photosensitive area: $3{\times}3mm^2$) for standard ${\gamma}$-ray sources, such as $^{133}Ba$, $^{22}Na$, $^{137}Cs$ and $^{60}Co$ were measured and compared. As a result, the energy resolutions of the proposed Ce:GAGG scintillation detector for g-rays, as measured using its spectroscopic properties, were found to be 13.5% for $^{133}Ba$ 0.356 MeV, 6.9% for $^{22}Na$ 0.511 MeV, 5.8% for $^{137}Cs$ 0.662 MeV and 2.3% for $^{60}Co$ 1.33 MeV.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.6
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• pp.1056-1063
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• 2006

Thermal evaporated 10 nm-Ni/l nm-Ir/(or polycrystalline)p-Si(100) and 10 nm-$Ni_{50}Co_{50}$/(or polycrystalline)p-Si(100) films were thermally annealed using rapid thermal annealing fur 40 sec at $300{\sim}1200^{\circ}C$. The annealed bilayer structure developed into Ni(Ir or Co)Si and resulting changes in sheet resistance, microstructure, phase and composition were investigated using a four-point probe, a scanning electron microscopy, a field ion beam, an X-ray diffractometer and an Auger electron spectroscope. The final thickness of Ir- and Co-inserted nickel silicides on single crystal silicon was approximately 20$\sim$40 nm and maintained its sheet resistance below 20 $\Omega$/sq. after the silicidation annealing at $1000^{\circ}C$. The ones on polysilicon had thickness of 20$\sim$55 nm and remained low resistance up to $850^{\circ}C$. A possible reason fur the improved thermal stability of the silicides formed on single crystal silicon substrate is the role of Ir and Co in preventing $NiSi_2$ transformation. Ir and Co also improved thermal stability of silicides formed on polysilicon substrate, but this enhancement was lessened due to the formation of high resistant phases and also a result of silicon mixing during high temperature diffusion. Ir-inserted nickel silicides showed surface roughness below 3 nm, which is appropriate for nano process. In conclusion, the proposed Ir- and Co- inserted nickel silicides may be superior over the conventional nickel monosilicides due to improved thermal stability.

• Journal of the Korean Vacuum Society
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• v.16 no.3
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• pp.161-166
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• 2007

Photovoltaic (PV) technology permits the transformation of solar light directly into electricity. For the last five years, the photovoltaic sector has experienced one of the highest growth rates worldwide (over 30% in 2006) and for the next 20 years, the average production growth rate is estimated to be between 27% and 34% annually. Currently the cost of electricity produced using photovoltaic technology is above that for traditional energy sources, but this is expected to fall with technological progress and more efficient production processes. A large scale production of solar grade silicon material of high purity could supply the world demand at a reasonably lower cost. A shift from crystalline silicon to thin film is expected in the future. The technical limit for the conversion efficiency is about 30%. It is assumed that in 2030 thin films will have a major market share (90%) and the share of crystalline cells will have decreased to 10%. Our research at Sungkyunkwan University of South Korea is confined to crystalline silicon solar cell technology. We aim to develop a technology for low cost production of high efficiency silicon solar cell. We have successfully fabricated silicon solar cells of efficiency more than 16% starting with multicrystalline wafers and that of efficiency more than 17% on single crystalline wafers with screen printing metallization. The process of transformation from the first generation to second generation solar cell should be geared up with the entry of new approaches but still silicon seems to remain as the major material for solar cells for many years to come. Local barriers to the implementation of this technology may also keep continuing up to year 2010 and by that time the cost of the solar cell generated power is expected to be 60 cent per watt. Photovoltaic source could establish itself as a clean and sustainable energy alternate to the ever depleting and polluting non-renewable energy resource.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.419-420
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• 2009

The authors fabricated the nanostructural patterns on the surface of SiN antireflection layer of polycrystalline Si solar cell and the surface of crystalline Si wafer using anodic aluminum oxide (AAO) masks in an inductively coupled plasma(ICP) etching process. The AAO nanopattern mask has the hole size of about 70~80nm and an ave rage lattice constant of 100nm. The transferred nano-patterns were observed by the scanning electron microscope (SEM) and the enhancement of solar cell efficiency will be presented.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.1
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• pp.27-40
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• 1997

The heat in Czochralski method is transfered by all transport mechanisms such as convection, conduction and radiation and convection is caused by the temperature difference in the molden pool, the rotations of crystal or crucible and the difference of surface tension. This study delvelops the simulation model of Czochralski growth by using the finite difference method with fixed grids combined with new latent heat treatment model. The radiative heat transfer occured in the surfce of the system is treated by calculating the view factors among surface elements. The model shows that the flow is turbulent, therefore, turbulent modeling must be used to simulate the transport phenomena in the real system applied to 8" Si single crystal growth process. The effects of a cusp magnetic field imposed on the Czochralski silicon melt are studied by numerical analysis. The cusp magnetic field reduces the natural and forced convection due to the rotation of crystal and crucible very effectively. It is shown that the oxygen concentration distribution on the melt/crystal interface is sensitively controlled by the change of the magnetic field intensity. This provides an interesting way to tune the desired O concentration in the crystal during the crystal growing.

• Journal of the Korean Ceramic Society
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• v.29 no.4
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• pp.273-282
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• 1992

The effects of intrinsic and extrinsic gettering on the formation of microdefects in the wafer and on the electrical performance at near-surfaces of three different oxygen-bearing Czochralski silicon single crystal wafers were investigated by varying the combinations of the pre-heat treatments and the phosphorus diffusion through the back-surface of the wafers. The wafers which had less than 10.9 ppma of oxygen formed no gettering zones irrespective of any pre-heat treatments, while the wafers which had more than 14.1 ppma of oxygen and were treated by Low+High pre-heat treatments generated the gettering zone comprising oxygen precipitates, staking faults, and dislocation loops. The effects of extrinsic gettering by phosphorus diffusion were evident in all samples such that the minority carrier lifetimes were increased and junction leakage currents were decreased. However, the total gettering effects among the different pre-heat treatments did not necessarily correspond to the gettering structure revealed by synchrotron radiation section topograph.