• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.5
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• pp.503-510
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• 1989

This paper represents a method which construct Combinational Mutiple Valued Logic circuits. First, it constructs Combinational Multiple Valued Logic Cell as the input variable, Then, it can be applied to the general case by expanding ti, thus these series of process is simple and regular. The construction theory of Combinational Multiple Valued Logic circuits, representes here has regularity, simplicity and modularity, especially, in case imput variables are incresed this theory also has characteristics of expansion.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.03a
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• pp.103-106
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• 1998

본 논문은 다치논리와 신경망을 융합한 다치 뉴로 모델을 제안한다. 다치논리를 이용하여 다치 연산을 위한 알고리즘을 제안하고, 다치-OR, 다치-AND, 다치-NOT 회로를 이용한 다치 뉴로 시스템을 구성하고, 모의 실험을 통하여 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.1
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• pp.42-47
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• 1985

An efficient logic circuit for realizing the function which has output of 1 diagonaly and design for multivalued logic circuit using with ROM structure which has two output at once are presented. The circuits presented are suited for the circuit design of a symmetric multivalued truth tables and the circuit design of multivalued truth tables with many independent variables. Also, they are applied to the multivalued truth tables of Galois field(GF).

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1997.11a
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• pp.220-223
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• 1997

다치 논리는 2치 논리에 비하여 동일 정보량을 처리하는데, 고속 처리가 가능하고, 정보의 기억 밀도가 크며, 논리 회로 실현시 입.출력 단자수가 감소하는 등의 장점을 가지고 있다. 본 논문에서는 이러한 다치 논리가 가지는 장점을 이용하여, 영상 처리시 필요한 농도를 2치가 아닌 다치로 농도표현을 하고자 한다.

• The KIPS Transactions:PartA
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• v.14A no.2
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• pp.107-116
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• 2007

In this paper, we present a method on the construction of multiple-valued circuits using Reed-Muller Expansions(RME). First, we discussed the input output interconnection of multiple valued function using Perfect Shuffle techniques and Kronecker product and designed the basic cells of performing the transform matrix and the reverse transform matrix of multiple valued RME using addition circuit and multiplication circuit of GF(4). Using these basic cells and the input-output interconnection technique based on Perfect Shuffle and Kronecker product, we implemented the multiple valued logic circuit based on RME. The proposed design method of multiple valued RME is simple and very efficient to reduce addition circuits and multiplication circuits as compared with other methods for same function because of using matrix transform based on modular structures. The proposed design method of multiple valued logic circuits is simple and regular for wire routing and possess the properties of concurrency and modularity of array.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.271-280
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• 2002

In this paper, the input-output interconnection method of the multiple-valued signal processing circuit using Perfect Shuffle technique and Kronecker product is discussed. Using this method, the circuit design method of the multiple-valued Reed-Muller Expansions (MRME) which can process the multiple-valued signal easily on finite fields GF$(p^m)$ is presented. The proposed input-output interconnection methods show that the matrix transform is an efficient and the structures are modular. The circuits of multiple-valued signal processing of MRME on GF$(p^m)$ design the basic cells to implement the transform and inverse transform matrix of MRME by using two basic gates on GF(3) and interconnect these cells by the input-output interconnection technique of the multiple-valued signal processing circuits. The proposed multiple-valued signal processing circuits that are simple and regular for wire routing and possess the properties of concurrency and modularity are suitable for VLSI.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.278-281
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• 1999

In this paper, Squential circuit was implemented by decision diagram that can analyze and test large amount of functions easily. First of all, Memery device of multiple valued squential circuit was used D F/F, implemented with CMOS current mode. The opreation property of this circuit involved by PSPICE simulation. The result of Decision Diagram sequential circuit is simple and regular for selecting wire routing and posesses the property of analyze, testing. so it suitable for VLSI implementation.