• Korean Journal of Materials Research
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• v.22 no.4
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• pp.190-194
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• 2012

The formation of high-quality polycrystalline silicon (poly-Si) on relatively low cost substrate has been an important issue in the development of thin film solar cells. Poly-Si seed layers were fabricated by an inverse aluminum-induced crystallization (I-AIC) process and the properties of the resulting layer were characterized. The I-AIC process has an advantage of being able to continue the epitaxial growth without an Al layer removing process. An amorphous Si precursor layer was deposited on Corning glass substrates by RF magnetron sputtering system with Ar plasma. Then, Al thin film was deposited by thermal evaporation. An $SiO_2$ diffusion barrier layer was formed between Si and Al layers to control the surface orientation of seed layer. The crystallinity of the poly-Si seed layer was analyzed by Raman spectroscopy and x-ray diffraction (XRD). The grain size and orientation of the poly-Si seed layer were determined by electron back scattering diffraction (EBSD) method. The prepared poly-Si seed layer showed high volume fraction of crystalline Si and <100> orientation. The diffusion barrier layer and processing temperature significantly affected the grain size and orientation of the poly Si seed layer. The shorter oxidation time and lower processing temperature led to a better orientation of the poly-Si seed layer. This study presents the formation mechanism of a poly seed layer by inverse aluminum-induced crystallization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.34-41
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• 2010

We proposed the new pixel compensation circuit with high aperture ratio and the driving method for the large-area, low-power AMOLED applications in this study. We designed with the low-temperature poly-silicon(LTPS) thin film transistors(TFTs) that has poor uniformity but good mobility and stability. To lower the error rate of the pixel circuit and to improve the aperture ratio for bottom emission method, we simplified the pixel compensation circuit. Because the proposed pixel compensation circuit with high aperture ratio has very low contrast ratio for conventional driving methods, we proposed the new driving method and circuit for high contrast ratio. Black data insertion was introduced to improve the characteristics for moving images. The pixel circuit was designed for 19.6" WXGA bottom-emission AMOLED panel, and the average aperture ratio of the pixel circuit is improved from 33.0% to 41.9%. For the TFT's $V_{TH}$ variation of ${\pm}0.2\;V$, the non-uniformity and contrast ratio of the designed panel was estimated under 6% and over 100000:1 respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.368-368
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• 2016

그래핀(Graphene)은 탄소 원자가 6각 구조로 이루진 2차원 알려진 물질 중 가장 얇은(0.34 nm) 두께의 물질이며 그 밴드구로조 인해 우수한 전자 이동도($200000cmV^{-1}s^{-1}$)를 가지고 있며, 이외에도 기계적, 화학적으로 뛰어난 특성을 가진다. 대면적화 된 그래핀을 성장시키기 위한 방법으로는 화학적 기상 증착법(Chemical Vapor Deposition)이 있다. 하지만 실제 여러 전이금속에서 합성되는 그래핀은 다결정으로, 서로 다른 면 방향을 가진 계면에서 전자의 산란이 일어나며, 고유의 우수한 특성이 저하되게 된다. 따라서 전자소재로 사용되기 위해서는 단결정의 대면적화 된 그래핀에 대한 연구가 지속적으로 이루어지고 있다. 앞서의 두 문제점 중, 단결정의 그래핀 합성에 크게 영향을 미치는 요인으로는 크게 합성 온도, 촉매 기판의 탄소 용해도, 촉매 표면에서의 탄소 원자의 확산성이 있다. 본 연구에서는 구리, 니켈, 실리콘에 비해 탄소 용해도가 낮으며, 탄소 원자의 높은 확산성으로 인해 단결정의 단층 그래핀을 합성에 적합하다고 보고된 저마늄(Germanium) 기판을 사용하여 그래핀을 합성하였다. 단결정의 그래핀을 성장시키기 위해 메탄(Methane; $CH_4$)가스의 주입량과 수소 가스의 주입량을 제어하여 성장 속도를 조절 하였으며, 성장하는 그래핀의 면방향을 제어하고자 하였다. 표면의 산화층(Oxidized layer)을 제거하기 위하여 불산(Hydrofluoric acid)를 사용하였다. 불산 처리 후 표면의 변화는 원자간력현미경(Atomic force microscopipe)을 통하여 분석하였다. 합성된 그래핀의 특성을 저 에너지 전자현미경(Low energy electron microscopy), 광전자 현미경(Photo emission electron microscopy), 라만 분광법(Raman spectroscopy), 원자간력현미경(Atomic force microscopy)와 투과전자현미경 (transmission electron microscopy)을 이용하여 기판 표면의 구조와 결정성을 분석하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.48-55
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• 2016

Ambient-light sensor system, which changes the brightness of a display as ambient light change, was studied to reduce the power consumption of the mobile applications such as note PC, tablet PC and smart phone. The ambient-light sensor system should be integrated on a display panel to improve the complexity and cost of mobile applications, so the ambient-light sensor and readout circuit was integrated on a display panel using low-temperature poly-silicon thin film transistors (LTPS-TFT). We proposed the new compensation method to correct the panel-to-panel variation of the ambient-light sensors, without additional equipment. We designed and investigated the new readout circuit with the proposed compensation method and the analog-to-digital converter for the final digital output of ambient light. The readout circuit has very simple structure and control timing to be integrated with LTPS-TFT, and the input luminance ranges from 10 to 10,000 lux. The readout rate is 100 Hz, and maximum differential non-uniformity with 20 levels of the final output below 0.5 LSB.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.1
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• pp.3-9
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• 2009

Although Active matrix organic light emitting diode (AMOLED) display has a better image quality in terms of viewing angle, contrast ratio, and response time than liquid crystal displays (LCDs), it still has some critical issues such as lifetime, residual images, and brightness non-uniformity due to non-uniformity in electrical characteristics of driving TFTs and IR drops on supplied power line. Among them, we improved irrecoverable residual images of AMOLED displays which is mainly related to the hysteresis characteristics of driving TFTs. We consider four kinds of surface treatment conditions before gate oxide deposition for improving hysteresis characteristics. We can reduce the hysteresis level of p-channel TFT to 0.23 V, interface trap states between the poly-Si layer and gate insulator to $3.11{\times}10^{11}cm^{-2}$, and output current variation of p-channel TFT to 3.65 % through the surface treatment using ultraviolet light and H2 plasma. Therefore, the recoverable residual image problem of AMOLED displays can be improved by surface treatment using ultraviolet light and $H_2$ plasma.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.173-176
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• 2004

In this study we investigated post ELA(Excimer Laser Annealing) effect on SMC (Silicide Mediated Crystalization) poly-Si (Polycrystalline Silicon) to improve the characteristics of poly-Si. Combining SMC and XeCl ELA were used to crystallize the a-Si (amorphous Silicon) at various ELA energy density for LTPS (Low Temperature Polycrystalline Silicon). We fabricated the conventional SMC poly-Si with no SPC (Solid Phase Crystallization) phase using UV heating method[1] and irradiated excimer laser on SMC poly-Si, so called SMC-ELA poly-Si. After using post ELA we can get better surface morphology than conventional ELA poly-Si and enhance characteristics of SMC poly-Si. We also observed the threshold energy density regime in SMC-ELA poly-Si like conventional ELA poly-Si.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.34-41
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• 1984

MOEN/MO double layer which is to be used It)r the RMOS (refractory metal oxide semiconductor) gate material has been fabricated by means of low temperature reactive sputtering in N2 and Ar mixture. Good Mo2N film was obtained in the volumetric mixture of Ar:N2=95:5. The sheet resistance of the fabricated Mo7N film was about 1.20 - 1.28 ohms/square, which is about an order of magnitude lower than that of polysilicon film, and this would enable to improve the operational speed of devices fabricated with this material. When PSG (phosphorus silicate glass) was used as impurity diffusion source for the source and drain of the RMOSFET in the N2 atmosphere at about 110$0^{\circ}C$, the Mo2N was reduced to Mo resulting in much smaller sheet resistance of about 0.38 ohm/square. The threshold voltage of the RMOSFET fabricated in our experiment was - 1.5 V, and both depletion and enhancement mode RMOSFETs could be obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.31-37
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• 2000

In the case of metal-induced lateral crystallization (MILC) for low temperature poly-Si TFT, offset length between Ni-thin film and the sides of gate could be modified to control the location of MILC boundary. Electrical characteristics were compared to analyze the effect of MILC boundary that was located either in or out of the channel region of the TFT. By removing the MILC boundary from channel region, on current, subthreshold slope and leakage current properties could be improved. When MILC boundary was located in the channel region, leakage current was reduced with electrical stress biasing. The amount of reduction increased as the channel width increased, but it was independent of the channel length.

• Journal of the Korean Vacuum Society
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• v.12 no.2
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• pp.130-135
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• 2003

Polycrystalline silicon thin films have been used for low cost thin film device application. However, it was very difficult to fabricate high performance poly-Si at a temperature lower than $600^{\circ}C$ for glass substrate because the crystallization process technologies like conventional solid phase crystallization (SPC) require the number of high temperature (600-$1000^{\circ}C$) process. The objective of this paper is to grow poly-Si on flexible substrate using a rapid thermal crystallization (RTC) of amorphous silicon (a-Si) layer and make the high temperature process possible on molybdenum substrate. For the high temperature poly-Si growth, we deposited the a-Si film on the molybdenum sheet having a thickness of 150 $\mu\textrm{m}$ as flexible and low cost substrate. For crystallization, the heat treatment was performed in a RTA system. The experimental results show the grain size larger than 0.5 $\mu\textrm{m}$ and conductivity of $10^{-5}$ S/cm. The a-Si was crystallized at $1050^{\circ}C$ within 3min and improved crystal volume fraction of 92 % by RTA. We have successfully achieved a field effect mobility over 67 $\textrm{cm}^2$/Vs.