• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.1.1-11
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• 1974

A general and systematic method of organizing two-dimensional flexible cellular array which is capable of reclizing arbitrary combinational switching function is developed. A set of n functions of n variables is transformed to revalued functions of one variable. This set of functions form a semigroup under the normal operation which is defined in this paper. A systematic method of generating any functions using three base functions is presented. Three basic networks which are capable of realizing three base functions are designed using only one one-dimensional array. The algorithm is presented for lealizing arbitrary combinational switching functions by organizing this basic array in two.dimensional cellular array and by appropriately setting the parameters or the edge of the array.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.72-79
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• 2003

This paper proposes a 32${\times}$32 Modified Booth multiplier using CMOS multiple-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 67.1% and 37.3%, compared with that of the voltage mode binary multiplier and the previous multiple-valued logic multiplier, respectively. The multiplier is designed with a 0.35${\mu}{\textrm}{m}$ standard CMOS technology at a 3.3V supply voltage and unit current 10$mutextrm{A}$, and verified by HSPICE. The multiplier has 5.9㎱ of propagation delay time and 16.9mW of power dissipation. The performance is comparable to that of the fastest binary multiplier reported.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.954-961
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• 2010

Stream cipher was worse than block cipher in terms of security, but faster in execution speed as an advantage. However, since so far there have been many algorithm researches about the execution speed of block cipher, these days, there is almost no difference between them in the execution speed of AES. Therefore an secure and fast stream cipher development is urgently needed. In this paper, we propose a 32bit output fast stream cipher, AA32, which is composed of ASR(Arithmetic Shifter Register) and simple logical operation. Proposed algorithm is a cipher algorithm which has been designed to be implemented by software easily. AA32 supports 128bit key and executes operations by word and byte unit. As Linear Feedback Sequencer, ASR 151bit is applied to AA32 and the reduction function is a very simple structure stream cipher, which consists of two major parts, using simple logical operations, instead of S-Box for a non-linear operation. The proposed stream cipher AA32 shows the result that it is faster than SSC2 and Salsa20 and satisfied with the security required for these days. Proposed cipher algorithm is a fast stream cipher algorithm which can be used in the field which requires wireless internet environment such as mobile phone system and real-time processing such as DRM(Digital Right Management) and limited computational environments such as WSN(Wireless Sensor Network).

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.661-663
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• 2002

현대의 Deep-Submicron Technology(DSM)에선 배선에 관련된 문제, 예를 들어 crosstalk이나 노이즈 등이 큰 문제가 된다. 그리하여, 배선은 논리 구성요소들보다 더욱 중요한 위치를 차지하게 되었다. 우리는 이러한 배선을 고려하여 연산식을 최적화하기 위해 carry-save-adder(CSA)를 이용한 모듈 함성 알고리즘을 제시한다. 즉, 상위 단계에서 생성 된 규칙적인 배선 토폴로지를 유지하며 CSA간의 배선을 좀더 향상시키는 최적의 알고리즘을 제안한다. 우리는 우리의 이러한 방법으로 생성된 지연시간이 [1]에 가깝거나 거의 근접하는 것을 많은 testcase에서 보이며(배선을 포함하지 않은 상태에서), 그리고 그와 동시에 최종 배선의 길이가 짧고 규칙적인 구조를 갖는것을 보인다.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2002.11a
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• pp.468-478
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• 2002

고품질의 영상 압축기인 JPEG2000의 기본 압축 코덱인 EBCOT(Embedded Block Coding With Optimized Truncation)를 설계하였다. 영상 압축기에서 Context 추출 구현을 위하여 코드블록(Code block)으로 분할하고, 비트플랜(Bit-Plane)코딩을 했으며, 3가지 패스 그룹으로 분리한 후 ZC, RLC, MR, SC를 하였다. 산술부호화는 덧셈 연산과 쉬프트 연산만을 사용하는 MQ-coder를 사용하였으며, Context들의 누적 확률을 추정하여 테이블을 작성하였고, 압축데이터를 산출하였다. 영상 압축을 위한 엔트로피 코더의 하드웨어 구현은 VHDL를 이용하여 설계를 하고, Synopsys사의 논리 회로 합성 도구를 사용하여 합성을 하였으며, Altera사의 FLEX 10K250 Device를 이용하여 FPGA로 구현하였다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.11a
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• pp.468-478
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• 2002

고품질의 영상 압축기인 JPEG2000의 기본 압축 코덱인 EBCOT(Embedded Block Coding With Optimized Truncation)를 설계하였다. 영상 압축기에서 Context 추출 구현을 위하여 코드블록(Code block)으로 분할하고, 비트플랜(Bit-Plane)코딩을 했으며, 3가지 패스 그룹으로 분리한 후 ZC, RLC, MR, SC를 하였다. 산술부호화는 덧셈 연산과 쉬프트 연산만을 사용하는 MQ-coder를 사용하였으며, Context들의 누적 확률을 추정하여 테이블을 작성하였고, 압축데이터를 산출하였다. 영상 압축을 위한 엔트로피 코더의 하드웨어 구현은 VHDL를 이용하여 설계를 하고, Synopsys사의 논리 회로 합성 도구를 사용하여 합성을 하였으며, Altera사의 FLEX 10K250 Device를 이용하여 FPGA로 구현하였다.

• Communications of Mathematical Education
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• v.9
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• pp.63-72
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• 1999

수학의 가장 기본적인 요소인 수 개념과 감각의 형성과정에서 자리값에 대한 이해는 필수적이다. 또한 자리 값의 개념을 지도하기 위해서는 수와 연산지도가 통합되어야 하며, 논리적 사고력을 신장의 한 요소인 계산 알고리즘이 유의미한 학습되기 위해서는 자리값에 대한 이해가 바탕이 되어야 한다. 수에 대한 개념적 지식이 불충분한 상태에서 양을 수치화 하거나 지필 위주로 계산 알고리즘을 기계적으로 적용함으로 해서 발생하는 수와 연산학습의 결손을 줄이기 위해 본 연구에서는 수 개념과 감각을 기르기 위해 자리값 지도 방안에 대해서 알아보고자 한다.

• Journal of the Korean Chemical Society
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• v.46 no.6
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• pp.569-580
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• 2002

The purpose of this study was to analyze the problem-solving process of student's compensation con-cept.For this purpose, verbal interactions during activities were audio-taped, transcribed, and analyzed. And classroom observation and interview with students were carried out. Students who were superior in mathematical operations tended to explain compensation concept using proportionality. On the other hand, students who had low level of conservation concept can not connect 'relation of two variables' with 'conservation of equilibrium' at the formation process of com-pensation concept. Students who succeed in the formation of compensation concept showed high level of conservation concept. To promote the formation of compensation concept, it is necessary that how to develop proportional concept and conservation concept as closely related with compensation concept should be studied.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.347-356
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• 2003

The OCT algorithm needs efficient hardware architecture to compute inner product. The conventional methods have large hardware complexity. Because of this reason. a computation sharing multiplier was proposed for implementing inner product. However, the existing multiplier has inefficient hardware architecture in precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we proposed a new efficient computation sharing multiplier and applied it to implementation of 1-D DCT processor. The comparison results show that the new multiplier is more efficient than an old one when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using the proposed multiplier is more high performance than typical design methods.

• The Journal of Korean Association of Computer Education
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• v.7 no.1
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• pp.27-35
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• 2004

Software documents consist of a number of objects and relationships between them, and structure of documents can be changed frequently. In the existing software version management models, changes in one object may be propagated to other objects unnecessarily. In this paper, we propose an efficient version management model for software objects based on history of operations applied to software objects. Operations applied to objects are recorded in the operation history, and those are used to retrieve versions of a document. Because versions of objects are stored and retrieved using the operation delta, it is not required to compare versions of a document to extract delta during check-in process. In addition, it can manage changes of structure of objects efficiently because it supports not only object creation, deletion, and update operation but also object move operation.