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http://dx.doi.org/10.3745/KIPSTA.2003.10A.4.347

Design of 1-D DCT processor using a new efficient computation sharing multiplier  

Lee, Tae-Wook (울산대학교 대학원 전자공학과)
Cho, Sang-Bock (울산대학교 전기전자정보시스템공학부)
Publication Information
The KIPS Transactions:PartA / v.10A, no.4, 2003 , pp. 347-356 More about this Journal
Abstract
The OCT algorithm needs efficient hardware architecture to compute inner product. The conventional methods have large hardware complexity. Because of this reason. a computation sharing multiplier was proposed for implementing inner product. However, the existing multiplier has inefficient hardware architecture in precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we proposed a new efficient computation sharing multiplier and applied it to implementation of 1-D DCT processor. The comparison results show that the new multiplier is more efficient than an old one when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using the proposed multiplier is more high performance than typical design methods.
Keywords
Multiplier; Computation Sharing Multiplier; DCT Processor;
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