• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• The Journal of the Korea Contents Association
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• v.10 no.11
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• pp.341-351
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• 2010

Alarm system is very important for the safety of nuclear power plant. When alarm, operator refers alarm logic diagrams to identify the logical relationship between the alarm and its causes. This paper propose a system which tracks the logical path between alarm and its causes on the alarm logic diagrams of Wolsung nuclear power plant unit 3 & 4. And a grammar for the validation of logic diagrams expressed in 2 dimensional strings, and logical operations with 3 states to track alarm-cause paths and to display the state of logics are proposed. This system is on operation at Wolsung site.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.6
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• pp.589-594
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• 1992

This paper offers the simplification method of Multiple-Valued logic function based on M-AND,M-OR, NOT operation presented by Lukasiewicz. First in performing the simplification the result is different by the method to arrange Cube, the method to find the most effective adjacent term if, most of all, important in simplification. According to this method, the two-variable multiple-valued logic function given by truth table is decomposed. The simplification method in this paper proves that the number of devices and cost is considerably reduced comparing with the existing method 141 to realize the same logic functions.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.492-499
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• 1997

We proposed and studied an all-optical switching device made of a bent nonlinear waveguide and an all-optical logic gate made of a bent nonlinear Y-junction. The proposed devices as switch and a logic function are based on the evolution of nonlinear guided wave along a bent nonlinear waveguide. Since the characteristics of beam propagation depens on the nonlinearity, input power and bent angle of waveguide, the characteristics of output power transmission is calculated by variation the such parameters. Furthermore, by calculating the output power through the nonlinear media with different positions of detector in nonlinear media, we could find the ideal digital switching performance at specific position of detector and implement several all-optical logic functions (AND, OR, XOR) by power contrast between waveguide end and nonlinear media.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1794-1800
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• 2008

This paper presents a method of constructing the digital logic switching functions using PLA. First of all, we propose a MIN and MAX algebra arithmetic operation based on the Post algebra. And we discuss the T-gate which is used for realization of the MIN and MAX algebra arithmetic operation. Next, we discuss the MIN array and MAX array which are basic circuit of the PLA, also we discuss the literal property. For the purpose of the design for the digital logic switching functions using PLA, we Propose the variable partition, modular structure design, literal generator, decoder and invertor. The proposed method is the more compactable and extensibility.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11b
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• pp.58-60
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• 2005

대표적인 데이터마이닝 문제중의 하나인 연관규칙 탐사에는 지금까지 Apriori 기반의 많은 알고리즘들이 개발되어 왔다. 본 논문에서는 비트맵을 이용한 Apriori 알고리즘 구현방안을 제시한다. 우선, 핵심연산인 비트맵 논리곱(Bitmap AND)과 비트 카운팅(bit-counting)을 컴퓨터 CPU의 고급 기술을 이용해서 효과적으로 구현할 수 있음을 보인다. 또한, 트랜잭션 데이터를 비트맵으로 표현함으로써, 기존 Apriori와는 달리, 비트맵 논리곱 연산을 획기적으로 줄일 수 있는 방법을 제시한다. BAR의 이러한 구현기법을 통해, Apriori 기반의 최신 구현 방법에 비해, 성능이 최대 30배 정도 향상됨을 보인다.

• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.16-22
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• 2002

Effective component retrieval is very essential for component based software development. Facet scheme is one of typical component retrieval methods and is being widely researched. In this paper, an efficient algorithm which supports a query with logical operator NOT for more than one facet values is presented. With this new algorithm the complexity to calculate a weighted synaptic connectivity matrix is enhanced. Also a new scheme is presented to support a query with logical operators for multiple facets.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.3
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• pp.144-154
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• 2003

In this paper we present Logical Evolution method which is a new teaming algorithm for the concepts expressed as binary logic function. We try to solve some problems of Inductive Learning algorithms through Logical Evolution. First, to be less affected from limited prior knowledge, it generates features using the gained informations during learning process and learns the concepts with these features. Second, the teaming is done using not the whole example set but the individual example, so even if new problem or new input-output variables are given, it can use the previously generated features. In some cases these old features can make the teaming process more efficient. Logical Evolution method consists of 5 operations which are selected and performed by the logical evaluation procedure for feature generation and learning process. To evaluate the performance of the present algorithm, we make experiments on MONK data set and a newly defined problem.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1879_1880
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• 2009

본 논문에서는 제어상황에 따라 Type-1 Fuzzy Logic Controller가 선택적으로 rule을 사용하도록 rule 선택 알고리즘을 제안 한다. 그리고 이를 통해 연산 효율성을 높이는 방법에 관해 논한다. Type-1 Fuzzy Logic Controller는 기존의 제어기에 비해 설계하기 쉽고 성능이 더 뛰어나다. 그러나 제어 변수가 많아질수록 rule의 개수가 늘어나 연산량이 증가하게 된다. 연산량이 많아지면 고성능의 컴퓨터에서는 실시간 연산에 문제가 없으나 산업용 micro controller에서는 실시간 연산을 구현하는데 한계가 발생한다. 본 논문에서는 Type-1 Fuzzy Logic System의 논리구조에 근거하여 Type-1 Fuzzy Logic Controller의 연산량을 감소시킬 수 있는 알고리즘을 제안한다. 제안한 알고리즘은 제어상황에 따라 필요한 rule들만 선택적으로 제어값 도출을 위한 연산에 관여하도록 한다. Matlab 시뮬레이션을 통해 제안한 알고리즘의 유용성과 연산량을 실험하였다. 실험대상은 2륜 이동로봇으로 하였고 step 응답과 전/후진 시 결과를 관찰하였다. 실험 결과 제안한 알고리즘이 기존의 Type-1 Fuzzy Logic Controller에 비해 제어상황에 따라 필요한 rule들만 선택적으로 사용하는 것을 확인하였다. 결과적으로 연산 효율성이 향상되었다.