• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.9
• /
• pp.36-44
• /
• 2015

This paper proposes a low-complexity processor to correct vignetting and barrel distortion for wide-angle cameras. The proposed processor calculates the required correcting factors by employing the piecewise linear approximation so that the hardware complexity can be reduced significantly while maintaining correction quality. In addition, the processor is designed to correct the two distortions concurrently in a singular pipeline, which reduces the overall complexity. The proposed processor is implemented with 18.6K logic gates in a $0.11{\mu}m$ CMOS process and shows the maximum correction speed of 200Mpixels/s for correcting an image of which size is $2048{\times}2048$.

• Journal of Advanced Navigation Technology
• /
• v.14 no.5
• /
• pp.710-717
• /
• 2010

Even though there are 256 possible 1-qudit(1-variable quantum digit) functions in quaternary logic, the most useful functions are 4!=24 ones capable of representing in QGFSOP expressions by possible permuting of 0,1,2, and 3. In this paper, we propose a permutational literal(PL) representation and a QPL(Quaternary PL) gate which use the operands of a multiplicand A and an augend D in $Ax^C$+D(GF4) operation as a control variable of multi-cascaded PLs. And we also present new PL synthesis algorithms to synthesize QGFSOP expressed 24 (1-qudit) functions by applying three PL operators as ab(mutual permutation), + D(addition), and XA (multiplication). Finally architectures, circuits, and a CMOS implementation to realize proposed PL synthesis algorithms for $Ax^C$+D(GF4) functions are presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.247-250
• /
• 2008

RC6 which has different algorithm of encryption and decryption has been implemented to have the same algorithm between encryption' and decryption though inserting symmetry layer using simple rotate and logical operation. That means the half of whole RC6 round uses encryption algorithm and the rest of it uses decryption one and symmetry layer has been put into the middle of encryption and decryption. The proposed RC6 algorithm has no difference with the original one in the speed of process. However it is quite safe because by inserting symmetry layer the path of high probability which is needed for differential and linear analysis is cut oft so that it is hard to be analyzed. The proposed algorithm can be easily applied to the algorithm which has different encryption and decryption an make it same, and it can be good idea to be used to design a new block cipher algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.8A
• /
• pp.820-826
• /
• 2007

This paper proposes an enhanced degree computationless modified Euclid's(E-DCME) algorithm and its architecture for Reed-Solomon decoders. The proposed E-DCME algorithm has shorter critical path delay that is $T_{mult}+T_{add}+T_{mux}$ compared with the existing modified Euclid's algorithm and the degree computationless modified Euclid's(DCME) algorithm since it uses new initial conditions. The proposed E-DCME architecture employing a systolic array requires only 2t-1 clock cycles to solve the key equation without initial latency. In addition, the E-DCME architecture consisting of 3t basic cells has regularity and scalability since it uses only one processing element. The E-DCME architecture using the $0.18{\mu}m$ Samsung standard cell library consists of 18,000 gates.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.1
• /
• pp.54-61
• /
• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.18 no.2
• /
• pp.216-222
• /
• 2008

This paper proposed the multi characters detection algorithm using Color segmentation and the closing curve feature of LoG Operator in order to complement the demerit of the existing research which is weak in complexity of background, variety of light and disordered line and similarity of left and background color, etc. The proposed multi characters detection algorithm divided into three parts : The feature detection, characters format and characters detection Parts in order to be possible to apply to image of various feature. After preprocess that the new multi characters detection algorithm that proposed in this paper used wavelet, morphology, hough transform which is the synthesis logical model in order to raise detection rate by acquiring the non-perfection characters as well as the perfection characters with processing OR operation after processing each color area by AND operation sequentially. And the proposal algorithm is simulated with natural images which include natural character area regardless of size, resolution and slant and so on of image. And the proposal algorithm in this paper is confirmed to an excellent detection rate by compared with the conventional detection algorithm in same image.

• Journal of the Korea Society of Computer and Information
• /
• v.10 no.3 s.35
• /
• pp.237-247
• /
• 2005

Ubiquitous Sensor Network(USN) is the very core of a technology for the Ubiquitous environments. There is the weakness from various security attacks such that tapping of sensor informations, flowing of abnormal packets, data modification and Denial of Service(DoS) etc. And it's required counterplan with them. Especially it's restricted by the capacity of battery and computing. By reasons of theses. positively, USN security technology needs the lightweighted design for the low electric energy and the minimum computing. In this paper, we propose lightweight USN mutual authentication methology based on trust model to solve above problems. The proposed authentication model can minimize the measure of computing because it authenticates the sensor nodes based on trust information represented by subjective logic model. So it can economize battery consumption and resultingly increse the lifetime of sensor nodes.

• Journal of the Korea Computer Graphics Society
• /
• v.17 no.3
• /
• pp.9-19
• /
• 2011

Computing triangle-triangle intersections has been a fundamental task required for many 3D geometric problems. We propose a novel robust GPU algorithm to efficiently compute intersections in a large triangle set. The algorithm has three stages:k-d tree construction, triangle pair generation, and exact intersection computation. All three stages are executed on GPU except, for unsafe triangle pairs. Unsafe triangle pairs are robustly handled by CLP(controlled linear perturbation) on a CPU thread. They are identified by floating-point filtering while exact intersection is computed on GPU. Many triangles crossing a split plane are duplicated in k-d tree construction, which form a lot of redundant triangle pairs later. To eliminate them efficiently, we use a split index which can determine redundancy of a pair by a simple bitwise operation. We applied the proposed algorithm to computing 3D Minkowski sum boundaries to verify its efficiency and robustness.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.2
• /
• pp.453-461
• /
• 2010

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of embedded RISC core and a clock-gating algorithm using ODC (Observability Don't Care) operation to improve the power consumption of the core. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC core applied the proposed architecture is improved about 29% and dynamic power of the core using Chartered $0.18{\mu}m$ technology library is reduced by 16%.

• KIPS Transactions on Computer and Communication Systems
• /
• v.12 no.1
• /
• pp.1-8
• /
• 2023

It is impossible to overwrite on an already allocated page in SSDs, so whenever a write operation occurs a page replacement with a clean page is required. To resolve this problem, SSDs have an internal flash translation layer called FTL that maps logical pages managed by a file system of operating system to currently allocated physical pages. SSD pages discarded due to write operations must be recycled through initialization, but since the number of initialization times is limited the FTL provides a caching function to reduce the number of writes in addition to the page mapping function, which is a core function. In this study, we focus on the FTL cache methodologies reducing the number of page writes and analyze the related algorithms, and propose a write-only cache strategy. As a result of experimenting with the write-only cache using a simulator, it showed an improvement of up to 29%.