DOI QR코드

DOI QR Code

Analysis and Advice on Cache Algorithms of SSD FTL

SSD FTL 캐시 알고리즘 분석 및 제언

  • Hyung Bong, Lee ;
  • Tae Yun, Chung
  • 이형봉 (강릉원주대학교 컴퓨터공학과) ;
  • 정태윤 (강릉원주대학교 전자공학과)
  • Received : 2022.07.19
  • Accepted : 2022.10.11
  • Published : 2023.01.31

Abstract

It is impossible to overwrite on an already allocated page in SSDs, so whenever a write operation occurs a page replacement with a clean page is required. To resolve this problem, SSDs have an internal flash translation layer called FTL that maps logical pages managed by a file system of operating system to currently allocated physical pages. SSD pages discarded due to write operations must be recycled through initialization, but since the number of initialization times is limited the FTL provides a caching function to reduce the number of writes in addition to the page mapping function, which is a core function. In this study, we focus on the FTL cache methodologies reducing the number of page writes and analyze the related algorithms, and propose a write-only cache strategy. As a result of experimenting with the write-only cache using a simulator, it showed an improvement of up to 29%.

SSD는 이미 할당된 페이지에 대한 제자리 덮어쓰기가 불가능하므로 쓰기 연산이 있을 때마다 새로운 클린 페이지로의 대체가 필요하다. 이 문제를 지원하기 위해 SSD는 운영체제의 파일시스템에서 관리하는 논리 페이지를 현재 할당된 물리 페이지로 매핑하는 플래시 변환 계층인 FTL을 내부에 둔다. 쓰기 연산으로 버려진 SSD 페이지는 초기화 작업을 거쳐 재활용되어야 하는데, 그 횟수에 제한이 있기 때문에 FTL은 기본인 페이지 매핑 기능 외에 쓰기 횟수를 줄일 수 있는 캐시 기능을 제공한다. 이 연구에서는 쓰기 횟수를 줄이기 위한 FTL의 캐시 방법론에 집중하여 관련된 알고리즘들을 분석하고, 쓰기 전용 캐시 전략을 제안한다. 시뮬레이터를 사용하여 쓰기 전용 캐시를 실험한 결과 최대 29%의 개선 효과를 보였다.

Keywords

Acknowledgement

이 논문은 2022년도 정부(산업통상자원부)의 재원으로 한국산업기술진흥원 지원을 받아 연구되었음(P0015356, 상용화를 위한 개인 맞춤형 재활 헬스케어 디바이스 연동 시스템 개발).

References

  1. H. B. Lee and T. Y. Chung, "A comparative analysis on page caching strategies affecting energy consumption in the NAND flash translation layer," IEMEK Journal of Embedded Systems and Applications, Vol.13, No.3, pp.109-115, 2018. https://doi.org/10.14372/IEMEK.2018.13.3.109
  2. G. Zhu, J. H. Han, and Y. S. Son, "A preliminary study: Towards parallel garbage collection for NAND flash-based SSDs," IEEE Access, Vol.8, pp.223574-223587, 2020. https://doi.org/10.1109/ACCESS.2020.3043123
  3. T. S. Chung, D. J. Park, S. W. Park, D. H. Lee, S. W. Lee, and H. J. Song, "A survey of Flash Translation Layer," Journal of Systems Architecture, Vol.55, No.5-6, pp.332-343, 2009. https://doi.org/10.1016/j.sysarc.2009.03.005
  4. C. Matsui, A. Arakawa, C. Sun, and K. Takeuchi, "Write order-based garbage collection scheme for an LBA scrambler integrated SSD," IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol.25, No.2, pp.510-519, 2017. https://doi.org/10.1109/TVLSI.2016.2594200
  5. Y. Deng and J. Zhou, "Architectures and optimization methods of flash memory based storage systems," Journal of Systems Architecture, Vol.57, No.2, pp.214-227, 2011. https://doi.org/10.1016/j.sysarc.2010.12.003
  6. Samsung SSD_870_EVO [internet], https://semiconductor.samsung.com/resources/datasheet/Samsung_SSD_870_EVO_Data_Sheet_Rev1.1.pdf, 2021.
  7. A. Eisenman et al., "Flashield: A hybrid key-value cache that controls flash write amplification," in Proceedings of 16th USENIX Symposium on Networked Systems Design and Implementation(NSDI '19), pp.65-78, 2019.
  8. J. H. Kim, Computer Architecture-5th edition, Life and Power Press, pp. 284-288, 2019.
  9. S. Y. Park, D. W. Jung, J. U. Kang, J. S. Kim, and J. W. Lee, "CFLRU: A replacement algorithm for flash memory," in Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems(CASES'06), pp.234-241, 2006.
  10. H. B. Lee and T. Y. Chung, "Analysis and improvement of the DPW-LRU cache replacement algorithm for flash translation layer," IEMEK Journal of Embedded Systems and Applications, Vol.15, No.6, pp.289-297, 2020.
  11. H. Y. Jung, H. K. Shim, S. M. Park, S. Y. Kang, and J. H. Cha, "LRU-WSR: Integration of LRU and writes sequence reordering for flash memory," IEEE Transactions on Consumer Electronics, Vol.54, No.3, pp.1215-1223, 2008. https://doi.org/10.1109/TCE.2008.4637609
  12. Z. Li, P. Jin, X. Su, K. Cui, and L. Yue, "CCF-LRU: A new buffer replacement algorithm for flash memory," IEEE Transactions on Consumer Electronics, Vol.55, No.3, pp.1351-1359, 2009. https://doi.org/10.1109/TCE.2009.5277999
  13. P. Jin, Y. Ou, T. Harder, and Z. Li, "AD-LRU: An efficient buffer replacement algorithm for ash-based databases," Data Knowledge Engineering, Vol.72, pp.83-10, 2012.
  14. Y. Yuan, J. Zhang, G. Han, G. Jia, L. Yan, and W. Li, "DPW-LRU: An efficient buffer management policy based on dynamic page weight for flash memory in cyber-physical system," IEEE Access (Special Section on Distributed Computing Infrastructure for Cyber-Physical Systems), Vol.7, pp.58810-58821, 2019. https://doi.org/10.1109/access.2019.2914231
  15. W. H. Lee and J. H. Kwak, "2WPR: Disk buffer replacement algorithm based on the probability of reference to reduce the number of writes in flash memory," Journal of the Korea Society of Computer and Information, Vol.25, No.2, pp. 1-10, 2020.
  16. S. Wu, C. Du, H. Li, H. Jiang, Z. Shen, and B. Mao, "CAGC: A content-aware garbage collection scheme for ultra-low latency flash-based SSDs," in Proceedings of the IEEE International Parallel and Distributed Processing Symposium(IPDPS 2021), pp.162-171, 2021.
  17. S. Li, W. Tong, J. Liu, B. Wu, and Y. Feng, "Accelerating garbage collection for 3D MLC flash memory with SLC blocks," in Proceedings of the International Conference on Computer-Aided Design(ICCAD 2019), pp.162-171, 2021.
  18. Wikipedia, Hard disk drive performance characteristics [Internet], https://en.wikipedia.org/wiki/Hard_disk_drive_ performance_characteristics.
  19. UMass Trace Repository [Internet], http://traces.cs.umass.edu/index.php/Storage.