• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.5
• /
• pp.977-984
• /
• 2001

In this paper, Genetic-Fuzzy Algorithm for Inverted Pendulum is presented. This Algorithms is combine Fuzzy logic with the Genetic Algorithm. The Fuzzy Logic Controller is only designed to two inputs and one output. After Fuzzy control rules are determined, Genetic Algorithm is applied to tune the membership functions of these rules. To measure of performance of the designed Genetic-Fuzzy controller, Computer simulation is applied to Inverted Pendulum system. In the simulation, In the case of f[0.3, 0.3] Fuzzy controller is measured that maximum undershoot is $-5.0 \times 10^{-2}[rad]$, maximum undershoot is $3.92\times10^{-2}[rad]$ individually however, Designed algorithm is zero. The Steady state time is approximated that Fuzzy controller is 2.12[sec] and designed algorithm is 1.32[sec]. The result of simulation, Resigned algorithm is showed it's efficient and effectiveness for Inverted Pendulum system.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.2
• /
• pp.347-354
• /
• 2000

This paper presents the efficient mechanisms for concurrency control and writing authority control in collaborative writing system are represented by the tree structures which consist of the logical objects and the content objects connected to the terminal objects of trees. For concurrency control, we adopted the approach to extend the multiple-granularity-locking-scheme. This scheme allows us to lock any objects at each level of the hierarchy. We also defined the locking compatibility table by analysing the operations applicable to any objects at each level of the hierarchy. We finally suggest the extended-multiple-granularity-locking mechanism which uses the locking compatibilility table for deciding to lock an object. This scheme gives the benefit to maximize the possibility of concurrent accessing to the shared objects. In addition, we suggest a mechanism for writing authority control which prohibits the Non-Group users from modifying the shared objects based on the concept of Group/Non-Group The proposed mechanism allows us to protect copyright very reasonably.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.11
• /
• pp.144-151
• /
• 1998

In this paper, it is applied the analysis properties of mathematical morphology in order to process MIN/MAX operation on the basis of combination of predefined and weighted structuring element to FCNN having the structure of CNN combined with fuzzy logic between template and input/output. In this paper, as the fuzzy estimator is applied to the image including noise, thus it could be found the noise removal as well as the edge detection in the process of computer simulation. We could analyze and compare the results of edge detection using FCNN, CNN and median filter to which the erosion operation of morphology is applied. This paper could apply the static template and the variable template to FCNN using the quantization fuzzy function, in result we could confirm that the performance of FCNN got to improve in the process of computer simulation.

• The KIPS Transactions:PartC
• /
• v.8C no.1
• /
• pp.32-40
• /
• 2001

In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

• Journal of Korea Society of Industrial Information Systems
• /
• v.17 no.7
• /
• pp.71-79
• /
• 2012

Propose stream cipher Canon that need in Wireless sensor network construction that can secure confidentiality and integrity. Create Canon 128 bits streams key by 128 bits secret key and 128 bits IV, and makes 128 bits cipher text through whitening processing with produced streams key and 128 bits plaintext together. Canon for easy hardware implementation and software running fast algorithm consists only of simple logic operations. In particular, because it does not use S-boxes for non-linear operations, hardware implementation is very easy. Proposed stream cipher Canon shows fast speed test results performed better than AES, Salsa20, and gate number is small than Trivium. Canon purpose of the physical environment is very limited applications, mobile phones, wireless Internet environment, DRM (Digital Right Management), wireless sensor networks, RFID, and use software and hardware implementation easy 128 bits stream ciphers.

• The KIPS Transactions:PartA
• /
• v.18A no.6
• /
• pp.249-254
• /
• 2011

This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

• Spatial Information Research
• /
• v.8 no.1
• /
• pp.155-170
• /
• 2000

When we use R-Tree,a spatial index, to find objects matches some predicate, it often leads to an incorrect result of perform filtering step only with MBR. And , each candidates need to be inspected to conform if it really satisfies with given query, so called, 'refinement step'. In refinement step. we should perform disk I/O and expansive spatial operations which is the cause of increasing retrieval costs. Therefore, to minimize the number of candidate after filtering step, two-phase filtering methods were studied, but there was many problems such as inefficiency of filtering,maintenance of additional informations and reconstruction of data resulted from the loss of original information. So , in this paper, I propose an Extended R-Tree which provides ability to retrieve spatial objects only with some simple logical operations using Grid Table, truth table strong the information about the existence of spatial objects, in second filtering step. Consequently , this Extended R-Tree using Grid Filter has low cost of operation for filtering because of efficient second filtering step, and better filtering efficiency caused by high quality of approximation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.4
• /
• pp.675-683
• /
• 2009

RC6 which has different algorithm of encryption and decryption has been proposed to have the same algorithm between encryption and decryption through inserting symmetry layer using simple rotate and logical operation. That means the half of whole RC6 round uses encryption algorithm and the rest of it uses decryption one and symmetry layer has been put into the middle of encryption and decryption. The proposed RC6 algorithm has no difference with the original one in the speed of process. However it is quite safe because by inserting symmetry layer the path of high probability which is needed for differential and linear analysis is cut off so that it is hard to be analyzed. The proposed symmetry layer algorithm can be easily applied to the algorithm which has different encryption and decryption and make it same, and it can be good idea to be used to design a new block cipher algorithm.

• Journal of the Korea Computer Graphics Society
• /
• v.16 no.2
• /
• pp.9-17
• /
• 2010

Minkowski sum of two polyedra is an operation to compute the sum of all pairs of points contained in the polyhedra. It has been a very useful tool to solve many geometric problems arising in the areas of robotics, NC machining, solid modeling, and so on. However, very few algorithms have been proposed to compute Minkowski sum of polyhedra, because computing Minkowski sum boundaries is susceptible to roundoff errors. We propose an algorithm to robustly compute the Minkowski sum boundaries by employing the controlled linear perturbation scheme to prevent numerically ambiguous and degenerate cases from occurring. According to our experiments, our algorithm computes the Minkowski sum boundaries with the precision of $10^{-14}$ by perturbing the vertices of the input polyhedra up to $10^{-10}$.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.6
• /
• pp.34-42
• /
• 2014

This paper presents a low-complexity and high-throughput symbol detector for two-spatial-stream multiple-input multiple-output systems based on the modified maximum-likelihood symbol detection algorithm. In the proposed symbol detector, the cost function is calculated incrementally employing a multi-cycle architecture so as to eliminate the complex multiplications for each symbol, and the slicing operations are performed hierarchically according to the range of constellation points by a pipelined architecture. The proposed architecture exhibits low hardware complexity while supporting complicated modulations such as 256 QAM. In addition, various modulations and antenna configurations are supported flexibly by reconfiguring the pipeline for the slicing operation. The proposed symbol detector is implemented with 38.7K logic gates in a $0.11-{\mu}m$ CMOS process and its throughput is 166 Mbps for $2{\times}$3 16-QAM and 80Mbps for $2{\times}3$ 64-QAM where the operating frequency is 478 MHz.