• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.104-112
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• 2007

We developed a $7{\times}7$ parallel multiplier using LTPS-TFT. The proposed multiplier has multi-valued logic 7-3 Compressor with folding, 3-2 Compressor, and final carry propagation adder. Architecture minimized the carry propagation. And power consumption reduced by switching the current source to the circuit which is operated in current mode. The proposed multiplier improved PDP by 23%, EDP by 59%, and propagation delay time by 47% compared with Wallace Tree multiplier.

• Journal of the Korean Geographical Society
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• v.37 no.4
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• pp.371-384
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• 2002

It is very important to predict the environmental changes in the land-surface as a way of prevention of sustainable nature. This study investigated the difference between the predicted and actual data of Anmyeon-do from 1981 to 2000 through a fuzzy logic operation using multi-spectral image. According to literature survey, maps, and ground truth data, the types of land-use have changed due primarily to shore reclamation or wild land and grassland fostering before the eighties. After the mid-eighties, however, a number of private residents and commercial stores quickly have spreaded throughout beach resorts and quasi-agricultural and forest areas. Moreover, shore and community regions were severely damaged in the nineties with increased farmland, due to the development of tour places and expansion of city area. The predicted result of the environmental changes in the land-surface using the fuzzy logic operation was almost similar to the state of Anmyeon-do obtained through the satellite image. Particularly, the flat lands near the shore was predicted to change slightly. This area is largely under development, thereby raising concerns on the shore environment. Thus, this method is applicable to conducting research on the change in the land-surface.

• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.203-208
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• 2007

This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.41-45
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• 2017

This paper presents a method of constructing the efficiency multiple output switching function of the combinational logic systems. The proposed method reduce the optimized input variable pair and output variable pair after we obtained the final multiple output switching function which was time based multiplexing and obtained the common multiple end node extension logic decision diagram. Also the proposed method have an advantage of the cost, input-output node number, circuit simplification, increment of the arithmetic speed, and more regularity and extensibility compare with previous method.

• Journal of Korean Philosophical Society
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• v.139
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• pp.1-21
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• 2016

To quickly and accurately grasp the consistency and the true/false of sentence description, we may require the help of a computer. It is thus necessary to research and quickly and accurately grasp the consistency and the true/false of sentence description by computer processing techniques. This requires research and planning for the whole study, namely a plan for the necessary tables and those of processing, and development of the table of the five logic rules. In future research, it will be necessary to create and develop the table of ten basic inference rules and the eleven kinds of derived inference rules, and it will be necessary to build a DB of those tables and the computer processing of sentence logic using server programming JSP and client programming JAVA over its foundation. In this paper we present the overall research plan in referring to the logic operation table, dividing the logic and inference rules, and preparing the listed process sequentially by dividing the combination of their use. These jobs are shown as a variable table and a symbol table, and in subsequent studies, will input a processing table and will perform the utilization of server programming JSP, client programming JAVA in the construction of subject/predicate part activated DB, and will prove the true/false of a sentence. In considering the table prepared in chapter 2 as a guide, chapter 3 shows the creation and development of the table of the five logic rules, i.e, The Rule of Double Negation, De Morgan's Rule, The Commutative Rule, The Associative Rule, and The Distributive Rule. These five logic rules are used in Propositional Calculus, Sentential Logic Calculus, and Statement Logic Calculus for sentence logic.

• Journal of KIISE:Software and Applications
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• v.27 no.7
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• pp.691-701
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• 2000

Software documents consists of a number of objects and relationships between them, and structure of documents can be changed frequently. In this paper, we propose a version storage and consistency management model for fine-grained software objects based on operations applied to edit software objects. An object has an interface and can be updated only through operations defined in its interface. Operations applied to objects are recorded in the operation history, which is used to retrieve versions of a document and manage consistency between documents. Because versions of an object are stored and retrieved using the operation delta, it is not needed to compare versions of a document to extract delta and it is easy to identify the changes between versions in order to propagate the changes. Consistencies between documents are managed using dependencies between objects and kinds of the operations applied to the objects. Therefore unnecessary version propagation can be avoided. This paper presents a formal model of version retrieval and consistency management at the fine-grained level based on operations applied to the objects.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.29-36
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• 2016

Recently a new class of quantum gate called $NCV-{\mid}v_1$ > library with low cost realizable potentialities is being watched with keen interest. The $NCV-{\mid}v_1$ > MCT gate is composed of AND cascaded-$CV-{\mid}v_1$ > gates to control the target qudit and its adjoint gates to erase junk ones. This paper presents a new symmetrical duality library named $NCV^{\dag}-{\mid}v_1$ > library corresponding to $NCV-{\mid}v_1$ > library. The new $NCV^{\dag}-{\mid}v_1$ > library can be operated on OR logic under certain conditions. By using both the $NCV-{\mid}v_1$ > and $NCV^{\dag}-{\mid}v_1$ > libraries it is possible to realize MPMCT gates, SOP and POS type synthesis of quantum logic circuits with extremely low cost, and expect dual gate property caused by different operational attributes with respect to forward and backward operations.

• Journal for History of Mathematics
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• v.17 no.4
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• pp.45-64
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• 2004

The lambda calculus is a mathematical formalism in which functions can be formed, combined and used for computation that is defined as rewriting rules. With the development of the computer science, many programming languages have been based on the lambda calculus (LISP, CAML, MIRANDA) which provides simple and clear views of computation. Furthermore, thanks to the "Curry-Howard correspondence", it is possible to establish correspondence between proofs and computer programming. The purpose of this article is to make available, for didactic purposes, a subject matter that is not well-known to the general public. The impact of the lambda calculus in logic and computer science still remains as an area of further investigation.stigation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.57-67
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• 2005

Fast scalar multiplication of points on elliptic curve is important for elliptic curve cryptography applications. In order to vary field sizes depending on security situations, the cryptography coprocessors should support variable length finite field arithmetic units. To determine the effective variable length finite field arithmetic architecture, two well-known curve scalar multiplication algorithms were implemented on FPGA. The affine coordinates algorithm must use a hardware division unit, but the projective coordinates algorithm only uses a fast multiplication unit. The former algorithm needs the division hardware. The latter only requires a multiplication hardware, but it need more space to store intermediate results. To make the division unit versatile, we need to add a feedback signal line at every bit position. We proposed a method to mitigate this problem. For multiplication in projective coordinates implementation, we use a widely used digit serial multiplication hardware, which is simpler to be made versatile. We experimented with our implemented ECC coprocessors using variable length finite field arithmetic unit which has the maximum field size 256. On the clock speed 40 MHz, the scalar multiplication time is 6.0 msec for affine implementation while it is 1.15 msec for projective implementation. As a result of the study, we found that the projective coordinates algorithm which does not use the division hardware was faster than the affine coordinate algorithm. In addition, the memory implementation effectiveness relative to logic implementation will have a large influence on the implementation space requirements of the two algorithms.