• Journal of the Korea Computer Industry Society
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• v.8 no.4
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• pp.229-236
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• 2007

A factored form is a sum of products of sums of products, ..., of arbitrary depth. Factoring is the process of deriving a parenthesized form with the smallest number of literals from a two-level form of a logic expression. The factored form is not unique and described as either algebraic or Boolean. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube Boolean subexpressions from given two-level logic expression and to extract divisor/quotient pairs. Then, we derive extended divisor/quotient pairs, where their quotients are not cube-free, from the generated divisor/quotients pairs. We generate quotient/quotient pairs from divisor/quotient pairs and extended divisor/quotient pairs. Using the pairs, we make a matrix to generate Boolean factored form based on a technique of rectangle covering.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.31-37
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• 1997

This paper describes the design and implementation of 8 bit ALU graphic simulator which helps students who study the structure and operation course of general ALU. ALU of this paper consists of three parts, arithmetic circuit, logic circuit, and shifter. Each of them performs as follows. Arithmetic circuit performs arithmetic operation such as addition, subtraction, 1 increment, 1 decrement, 2's complement, logic circuit performs logic operation such as OR, AND, XOR, NOT, and shifter performs shift operation and transfers the result of circuits of arithmetic, logic to data bus. The instructions which relate to these basic ALU functions was selected from Z80 instructions and ALU circuit was designed with those instructions and this designed ALU circuit was implemented on graphic screen. And all state of this data operation course in ALU was showed by bit and logic gate unit.

• The Transactions of the Korea Information Processing Society
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• v.4 no.4
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• pp.1025-1034
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• 1997

Inference process of resolution-based automated reasoning easily consumes the memory of computer without giving any useful result by priducing lots of fruioless information which are not necessary for the conslusion. This paper suggests a control strategy for saving the space of computer memory and reducing the inference time. The strategy uses a restriction that comparatively irrelevant axioms do mot take pare in the resoluition. In order to analyze and determine the priorities of the input axioms of joning the inference process, the system employs the fuzzy relational products.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1998.12a
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• pp.137-147
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• 1998

RSA 암호 시스템에서 512비트 이상의 큰 정수 소수의 모듈라 멱승 연산이 필요하기 때문에 효율적인 암호화 및 복호화를 위해서는 모듈라 멱승 연산의 고속 처리가 필수적이다. 따라서 본 논문에서는 몫을 추정하여 모듈라 감소를 실행하고 carry-save 덧셈과 중간 곱의 크기를 제한하는 interleaved 모듈라 곱셈 및 감소 기법을 이용하여 모듈라 멱승 연산을 수행하는 고속 모듈라 멱승 연산 프로세서를 논리 자동 합성 기법을 바탕으로 하는 탑다운 선계 방식으로 VHDL을 이용하여 모델링하고 SYNOPSIS 툴을 이용하여 합성 및 검증한 후 XILINX XC4025 FPGA에 구현하여 성능을 평가 및 분석한다.

• Journal of Internet Computing and Services
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• v.9 no.3
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• pp.43-50
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• 2008

Authenticated Encryption scheme in RFID system is the important issue for ID security. But, implementing authenticated Encryption scheme in RFID systems is not an easy proposition and systems are often delivered for reasons of complexity, limited resources, or implementation, fail to deliver required levels of security. RFID system is so frequently limited by memory, performance (or required number of gates) and by power drain, that lower levels of security are installed than required to protect the information. In this paper, we design a new authenticated encryption scheme based on the EC(Elliptic Curve)'s x-coordinates and scalar operation. Our scheme will be offers enhanced security feature in RFID system with respect to user privacy against illegal attack allowing a ECC point addition and doubling operation.

• Journal of IKEEE
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• v.11 no.2
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• pp.83-88
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• 2007

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The 8${\times}$8 multiplier is designed with proposed MCML full adders and conventional full adders. The designed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. This circuit is designed with Samsung 0.35${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.7
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• pp.1234-1243
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• 1992

A systematic procedure to design fuzzy PID controllers is developed in this paper. The concept of local fuzzy control cell is proposed by introducing both an adequate global control rule and membership functions to simplify a fuzzy logic controller. Fuzzy decision is made by using algebraic product and parallel firing arithematic mean, and a defuzzification strategy is adopted for improving the computational efficiency based on nonfuzzy micro-processor. A direct method, transforming the typical output of quasi-linear fuzzy operator to the digital compensator of PID form, is also proposed. Finally, the proposed algorithm is applied to an DC-servo motor. It is found that this algorithm is systematic and robust through computer simulations and implementation of controller using Intel 8097 micro-processor.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.271-280
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• 2002

In this paper, the input-output interconnection method of the multiple-valued signal processing circuit using Perfect Shuffle technique and Kronecker product is discussed. Using this method, the circuit design method of the multiple-valued Reed-Muller Expansions (MRME) which can process the multiple-valued signal easily on finite fields GF$(p^m)$ is presented. The proposed input-output interconnection methods show that the matrix transform is an efficient and the structures are modular. The circuits of multiple-valued signal processing of MRME on GF$(p^m)$ design the basic cells to implement the transform and inverse transform matrix of MRME by using two basic gates on GF(3) and interconnect these cells by the input-output interconnection technique of the multiple-valued signal processing circuits. The proposed multiple-valued signal processing circuits that are simple and regular for wire routing and possess the properties of concurrency and modularity are suitable for VLSI.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.3
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• pp.115-122
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• 1985

In this paper, A decoder for the product of the (7, 4) cyclic code and the (3, 1) cyclic code was designed with less majority gates than other ordinary two-step majority-logic decoder using the same codes, then it was constucted in simple sturucture as a result of the use of a ROM as a mojority gate. It took 42 clock pulses to correct a received word(or 21bits) entirely. And so the decoding time in this decoding was multiplied by a factor of about 0.7 relative to the decoding time in the previous decoding in which two decoders and two-demensional word arrays were used together.