• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.7-16
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• 2000

This paper reports a methodology and its application for extracting cell capacitances and parasitic capacitances in a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitances, we employed finite element method (FEM), The three-dimensional DRAM cell structure is generated by solid modeling based on two-dimensional mask layout and transfer data. To obtain transfer data for generating three-dimensional simulation structure, topography simulation is performed. In this calculation, an exemplary structure comprising 4 cell capacitors with a dimension of $2.25{\times}1.75{\times}3.45{\mu}m^3$, 70,078 nodes with 395,064 tetrahedra were used in ULTRA SPARC 10 workstation. The total CPU time for the simulation was about 25 minutes, while the memory size of 201MB was required. The calculated cell capacitance is 24.34fF per cell, and the influential parasitic capacitances in a stacked DRAM cell are investigated.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.16-22
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• 2006

Gigabit transimpedance amplifiers are realihzed in submicron CMOS technologies for Gigabit Ethernet applications. The regulated cascode technique is exploited to enhance the bandwidth and noise performance simultaneously so that it can isolate the large input parasitic capacitance including photodiode capacitance from the determination of the bandwidth. The 1.25Gb/s TIA implemented in a 0.6um CMOS technology shows the measured results of 58dBohm transimpedance gain, 950MHz bandwidth for a 0.5pF photodiode capacitance, 6.3pA/sqrt(Hz) average noise current spectral density, and 85mW power dissipation from a single 5V supply. In addition, a 10Gb/s TIA is realized in a 0.18um CMOS incorporating the RGC input and the inductive peaking techniques. It provides 59.4dBohm transimpedance gain, 8GHz bandwidth for a 0.25pF photodiode capacitance, 20pA/sqrt(Hz) noise current spectral density, and 14mW power consumption for a single 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.109-114
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• 2004

This paper proposes an advanced circuit for the fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling of each sensor pixel. The fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Journal of IKEEE
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• v.24 no.3
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• pp.845-852
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• 2020

Developing standard cells for 3nm and beyond requires significant advances in the device and interconnect technology. Thus, it is very important to quantify the impact of the new technology in various aspects. In this paper, we perform a through analysis on the impact of Buried Power Rail (BPR) and Complementary FET (CFET) in the perspective of cell area and parasitics such as capacitance. We emphasize that CFET is a technology that realizes 4T and beyond for standard cell designs, but significant capacitance increases (+18.0%), compared to its counterpart technology (FinFET) cell, due to the increase of cell height in the Z-direction.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.168.1-168.1
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• 2013

고분자유기물로 사용되는 발광층에 탄소나노튜브를 합성하여 AC로 구동되는 고분자유기물소자를 제작하였다. 고분자유기물소자는 총 4개의 층(ITO/CRS/탄소나노튜브를 함유한 MEH-PPV/Al)으로 구성하였다. ITO가 코팅된 유리기판 위에 발광층을 보호하는 역할을 하는 절연층[cyanoethyl pullulan(CRS)], 유기발광물질인 poly[2-methoxy-5-(2-ethyl-hexyloxy)-1,4-phenylene-vinylene](MEH-PPV)에 탄소나노튜브의 함량을 조절하여 발광층으로 사용하였으며, 절연층과 발광층은 스핀코우터를 이용하여 증착하다. 마지막으로 thermal evaporator을 이용하여 Al을 증착하였다. 고분자유기물소자는 발광층에 함유된 탄소나노튜브에 함량에 따른 전압, 전류 그리고 밝기 특성을 분석하였다. 탄소나노튜브가 0.015wt% 함유된 고분자유기물소자에서 최대 밝기 특성과 낮은 소비전력을 얻을 수 있었다. 고분자유기물에 탄소나노튜브를 합성된 효과를 알아보기 위하여 임피던스분석을 통하여 고분자유기물소자의 저항, 캐패시턴스, 기생저항을 알아보았다. 고분자유기물소자의 캐패시턴스의 변화는 탄소나노튜브와 고분자 유기물(polymer-CNT matrix) 에서 생성되는 블록들이 매우 얇은 유전층을 구성할 것으로 예상되며 이는 micro-capacitance로 고분자유기물소자의 구동에 영향을 미치는 것으로 예상된다. AC구동 고분자유기물소자에 탄소나노튜브를 함유하여 높은 효율을 얻을 수 있는 장점으로 차세대 디스플레이나 조명으로 탄소나노튜브의 쓰임새를 기대해 본다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.8-18
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• 2000

We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.1
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• pp.70-77
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• 2005

A new converter to transfer energy from a low-voltage AC current source to a battery is proposed. It is focused to find operational modes of the converter. The low-voltage AC current source is an equivalent of the piezoelectric generator, which converts the mechanical energy to the electric energy. The converter consists of a full-bridge MOSFET rectifier and a MOSFET boost converter in order to make the converter small and efficient. The operational principle and modes of the converter are investigated with the consideration of effects of the parasitic capacitances of MOSFETs and diode. The results are proved with simulation studies using PSIM and Pspice.