• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.167-172
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• 2023

A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.195-195
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• 2011

플라즈마를 이용한 반도체 이온 주입 공정(Plasma Immersion Ion Implantation)에서 이온 도즈량(DOSE) 측정은 공정 신뢰성 및 재현성 확보를 위해 중요하다. 본 연구에서는 도즈량 측정을 위해 패러데이컵과 같이 측정 장비를 챔버에 직접 삽입 시키지 않고 챔버 외부에서 이온 주입을 위한 바이어스 전극의 직류 펄스 전압 및 전류 신호 측정을 통해 실시간으로 도즈량을 추출하는 방법을 개발하였다. 펄스 전압 신호에서 전압 신호 상승, 하강 시간에 의해 발생된 변위 전류와 플라즈마 발생 소스의 RF잡음등을 제거한 후 이온 포격으로 인한 2차 전자 방출 계수를 고려하여 펄스 동작 기간 추출을 통해 실시간으로 측정하는 알고리즘을 구현하였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.368-370
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• 2012

본 논문에서는 이중 홉 무선 네트워크에서 누적분포함수(cumulative distribution function) 기반 중계기 선택 기법을 제안한다. 제안된 기법은 수신 신호대잡음비(signal-to-noise ratio)의 누적분포함수 값에 따라 중계기를 선택한다. 본 논문에서는 제안한 기법의 중계기 공정성에 대한 분석을 통해 제안된 기법이 엄격하게 공정성을 달성할 수 있음을 보인다. 그리고 모의 실험에서는 round-robin 기법과 기회적 중계 기법을 제안된 기법과 총 타임 슬롯에 대한 각 중계기별 타임 슬롯 분배율, 평균 공정성, 불능확률 비교를 통해 제안된 기법이 엄격하게 공정성을 달성하는 것과, 기회적 중계 기법과 거의 동일한 기울기로 불능확률이 떨어지는 것을 확인한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2007.08a
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• pp.363-363
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• 2007

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.1
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• pp.53-60
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• 2010

This paper presents a novel gain control system composed of a feedback circuit, Two stage Low Noise Amplifier (LNA) using 0.18 um CMOS technology for 5.2 GHz. The feedback circuit consists of the seven function blocks: peak detector, comparator, ADC, IVE(Initial Voltage Elimination) circuit, switch, storage, and current controller. We focus on detecting signal and designing storage circuit that store the previous state. The power consumption of the feedback circuit in the system can be reduced without sacrificing the gain by inserting the storage circuit. The adaptive front-end system with the feedback circuit exhibits 11.39~22.74 dB gain, and has excellent noise performance at high gain mode. Variable gain LNA consumes 5.68~6.75 mW from a 1.8 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.430-433
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• 2017

This paper presents a S/C/X-band LNA MMIC with resistive feedback structure in 0.25 um GaN HEMT process. The GaN devices have advantages as a high output power device having high breakdown voltage, energy band gap and stability at high temperature. Since the receiver using the GaN device with high linearity can be implemented without a limiter, the noise figure of the receiver can be improved and the size of receiver module can be reduced. The proposed GaN LNA MMIC based on 0.25 um GaN HEMT device is achieved the gain of > 15 dB, the noise figure of < 3 dB, the input return loss of > 13 dB, and the output return loss of > 8 dB in the S/C/X-band. The current consumption of GaN LNA MMIC is 70 mA with the drain voltage 20 V and the gate voltage -3 V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1581-1586
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• 2012

In this paper, a novel resonator using ring type DGS is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator, and oscillator for 5.8GHz band is designed using proposed DGS resonator. The ring type DGS resonator is composed of DGS cell etched on ground plane under $50{\Omega}$ microstrip line. At the fundamental frequency of 5.8GHz, 7.6dBm output power and -82.7 dBc@100kHz phase noise have been measured for oscillator with ring type DGS resonator. The phase noise characteristics of oscillator is improved about 9.5dB compared to one using the general ${\lambda}/4$ microstrip resonator. Because it is possible that varactor diode or lumped capacitor is placed on the gaps of ring type DGS, resonant frequency can be controlled by bias voltage. We can design voltage controlled oscillator using proposed ring type DGS resonator. Thus, due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1538-1543
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• 2013

In this paper, a novel split ring resonator is proposed for improvement of phase noise characteristics that is weak point of oscillator using planar type microstrip line resonator. Oscillator using proposed split ring resonator is designed, it has improved phase noise characteristics. At the fundamental frequency of 5.8GHz, 7.22dBm output power and -83.5 dBc@100kHz phase noise have been measured for oscillator with split ring resonator. The phase noise characteristics of oscillator is improved about 9.7dB compared to one using the general ${\lambda}/4$ microstrip resonator. Next, we designed voltage controlled oscillator using proposed split ring resonator with varactor diode. The VCO has 125MHz tuning range from 5.833GHz to 5.845GHz, and phase noise characteristic is -118~-115.5 dBc/Hz@100KHz. Due to its simple fabrication process and planar type, it is expected that the technique in this paper can be widely used for low phase noise oscillators for both MIC and MMIC applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.220-223
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• 2016

This letter proposes a low noise amplifier which has low noise figure and high linearity simultaneously using a cascode structure with an additional transistor. The proposed structure minimizes the noise source by using optimizing transistor sizes and also improves linearity from the current bleeding technique. The device was fabricated in a $0.5{\mu}m$ GaAs pHEMT process and has noise figure of 1.1 dB, a voltage gain of 15.0 dB, an $OIP_3$ of 30.8 dBm and an input/output return loss of 11.6 dB/10.4 dB from 1.8 to 2.6 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.52-57
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• 2009

This paper presents a low-noise low-dropout linear regulator that is suitable for on-chip integration with RF transceiver ICs. In the bandgap reference, a stacked diode structure is adopted for saving silicon area as well as maintaining low output noise characteristic. Theoretical analysis for supporting the approach is also described. The linear regulator is fabricated in $0.18{\mu}m$ CMOS process. It operates with an input voltage range of 2.2 V - 5 V and provide the output voltage of 1.8 V and the output current up to 90 mA. The measured line and load regulation is 0.04%/V and 0.46%, respectively. The output noise voltage is measured to be 479 nV/$^\surd{Hz}$ and 186 nV/$^\surd{Hz}$ from 100 Hz and 1 kHz offset, respectively.