• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Proceedings of the Safety Management and Science Conference
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• 2000.11a
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• pp.63-71
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• 2000

대량생산체제를 위주로 했던 산업혁명 초기에는 원가계산방식이 비교적 수월하였다. 생산에 투입된 비용을 그대로 생산량으로 나누기만 하면 되었고 이 수치를 그대로 원가라고 간주하여도 기업이 존속하는데는 아무 영향이 없었다. 물론 이 때에도 간접비라는 것은 존재하였으나 그 비중이 미미했기에 이를 무시하여도 되었던 것이다. 그러나 그 때와 달리 지금은 기업환경은 다품종 소량생산, 고객 주문 생산 등의 다양한 형태로 변화되어 왔으며 유연생산시스템, 적시생산시스템 등과 같은 새로운 경영기법 및 생산관리 기법이 발달함에 따라 그간 무시되어 왔던 간접비가 오히려 직접비보다도 많아지는 현상이 생기게 되었다. 그래서 증가하는 간접비를 효과적으로 제품이나 서비스에 배부하여야 하는 필요성에서 연구가 시작되었고 그 결과로서 나온 원가계산방법이 활동기준원가계산시스템이다. 우리 나라에는 90년대 초반에 도입되어 여러기업이 시스템을 구축한 상태이며 이에 대한 사례를 연구한 논문도 발표되었다. 활동기준원가 계산시스템이 기존의 원가계산시스템보다 더 정교하다는 것은 많은 이미 많은 연구들에서 입증이 되었지만 그래도 실제 시스템의 구축에 있어서는 아직도 많은 연구과제가 남아있다. 본 연구는 시스템의 구축과정에서 핵심과정으로써 반드시 거쳐야 하는 활동분석단계에 관심을 두고 활동분석과정을 가능한 적은 비용으로 빠르게 수행하기 위한 방법을 모색하였다. 그 방법으로 선택한 것이 기존의 기업보유자료를 이용하여 활동분석을 수행하는 것으로 비록 활동분석데이터의 신뢰성에는 조금 부족한 면이 있을 수 있으나 기업보유자료가 활동분석과 개연성이 있음을 제시하고자 하였다. 한다.드가 전송한 패킷은 이전 셀 지역에 있는 에이전트가 새로운 셀 지역에 있는 이동 노드로 패킷을 재전송하여 전달하는 smooth 핸드오프 기능을 제공한다. 이전 셀 지역에 속한 외부 에이전트가 바인딩을 갱신하기 전에 송신 노드로부터 이동노드로 전달된 패킷이 있을 경우는 패킷을 저장하여 이후에 이동 노드의 위치 정보에 관한 바인딩 정보가 갱신되면 이러한 바인딩 정보에 따라 패킷을 재전송하는 버퍼기능도 제공한다. route optimization mobile IP는 기본적인 mobile IP에서의 복잡한 라우팅 문제를 해결하고, 핸드오프에서의 패킷 손실률을 최소화 한다.본 논문에서는 컴퓨터 시뮬레이션을 통해 smooth 핸드오프를 이용한 mobile IP의 성능을 분석한다. 일반적으로 데이터 트래픽 특성, 노드의 이동성, 바인딩 갱신시간, 버퍼관리 방법 등은 핸드오프 동안 mobile IP의 성능에 많은 영향을 미친다. 따라서 시뮬레이션 모델을 이용하여 다양한 트래픽 환경에서 위에 언급된 성능 파라미터들의 영향을 분석한다. 마지막으로 시뮬레이션 결과를 이용하여 mobile IP의 성능을 개선시키기 위한 방법을 제시한다. 제시하고자 한다.과로 여겨지며, 또한 혈청중의 ALT, ALP 및 LDH활성을 유의성있게 감소시키므로서 감잎 phenolic compounds가 에탄올에 의한 간세포 손상에 대한 해독 및 보호작용이 있는 것으로 사료된다.반적으로 홍삼 제조시 내공의 발생은 제조공정에서 나타나는 경우가 많으며, 내백의 경우는 홍삼으로 가공되면서 발생하는 경우가 있고, 인삼이 성장될 때 부분적인 영양상태의 불충분이나 기후 등에 따른

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.431-435
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• 2011

This paper presents optimized searching technique to improve the performance of H.264/AVC. The proposed CAVLC encoder uses forward and backward searching algorithm to compute the parameters. By zero-block skipping technique and pipelined scheduling, the proposed CAVLC encoder can obtain better performance. The experimental result shows that the proposed architecture needs only 66.6 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 13.8% than that of previous designs. The proposed CAVLC encoder was implemented using VerilogHDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 15.6K with 125Mhz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.28-33
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• 2006

An integrated 3.125Gbps clock and data recovery (CDR) circuit is presented. The circuit does not need a reference clock. It has a phase and frequency detector (PFD), which incorporates a bang-bang type 4X oversampling PD and a rotational frequency detector (FD). It also has a ring oscillator type VCO with four delay stages and three zero-offset charge pumps. With a proposed PD and m, the tracking range of 24% can be achieved. Experimental results show that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology. The measured recovered clock jitter (p-p) is about 14ps. The CDR has 1.8volt single power supply. The power dissipation is about 140mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1734-1740
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• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12A
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• pp.1380-1386
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• 2004

Future communication networks would consist of wired and wireless access networks where there would be various types of traffic services. To meet the QoS requirements of those various traffic services simultaneously, new QoS control schemes are required. Since they are simple to deploy, cheep to manage, and easy to support subscriber mobility, wireless access networks are considered here. In this paper, a wireless joint buffer management and scheduling (W-JoBS) scheme, which is a modified version of the original JoBS algorithm at error-prone wireless access networks, is proposed. W-JoBS scheme is for providing service fairness among traffic classes with service compensation and channel-state dependent packet scheduling schemes. With computer simulation, this proposed W-JoBS scheme is evaluated and the performance of W-JoBS is compared with that of the original JoBS.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.242-246
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• 2012

This paper presents an integrated low noise and highly linear wideband RF front-end for a digital terrestrial and cable TV tuner, which are used as a part of double-conversion TV tuner. The low noise amplifier (LNA) has a low noise figure and high linearity by adopting a noise canceling technique based on current amplification. The up-conversion mixer and SAW buffer have high linearity by employing a third order intermodulation cancellation technique. The proposed RF front-end is designed in a $0.18{\mu}m$ CMOS and draws 60 mA from a 1.8 V supply voltage. The RF front-end shows a voltage gain of 30 dB, an average single side-band noise figure of 4.2 dB, an IIP2 of 40 dBm, and an IIP3 of -4.5 dBm for the entire band from 48 MHz to 862Hz.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.55-60
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• 2014

For an high speed communication, a 40GHz VCO was implemented using a 0.11um standard CMOS technology. The mm-wave VCO was designed by a LC type using a spiral inductor, and a simplified architecture with buffers and a smart biasing technique were used to get a high performance. The frequency range of the proposed VCO is 34~40GHz which is suitable for mm-Wave communication system. It has an output power of -16dBm and 16% tuning range. And the phase noise is -100.33dBc/Hz at 1MHz offset at 38GHz fundamental frequency. The total power consumption of VCO including PADs is 16.8mW with 1.2V supply voltage. The VCO achieves the FOMT of -183.8dBc/Hz which is better than previous VOCs.