• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1727-1736
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• 2006

In a fuzzy control system to vocess fuzzy data in high-speed for intelligent systems, one of the important problems is the improvement of the execution speed in the fuzzy inference and defuzzification stages. Especially, it is more important to have high-speed operations in the consequent Pan and defuzzification stage. Therefore, in this paper, to improve the speedup of the fuzzy controllers for intelligent systems, we propose novel integer fuzzy operation method without mulitplications and divisions by only integer addition to convert real values in the fuzzy membership functions in the consequent part to integer grid pixels $(400{\times}30)$ without [0, 1] real operations. Also we apply the proposed system to the truck backer-upper control system. As a result, this system shows a real-time very high speed fuzzy control as compared as the conventional methods. This system will be applied to the real-time high-speed intelligent systems such as robot arm control.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.165-171
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• 2019

The study of the computer architecture has shown that major improvements in price-to-energy performance stems from domain-specific hardware development. This paper analyzes the tensor processing unit (TPU) ASIC which can accelerate the reasoning of the artificial neural network (NN). The core device of the TPU is a MAC matrix multiplier capable of high-speed operation and software-managed on-chip memory. The execution model of the TPU can meet the reaction time requirements of the artificial neural network better than the existing CPU and the GPU execution models, with the small area and the low power consumption even though it has many MAC and large memory. Utilizing the TPU for the tensor flow benchmark framework, it can achieve higher performance and better power efficiency than the CPU or CPU. In this paper, we analyze TPU, simulate the Python modeled OpenTPU, and synthesize the matrix multiplication unit, which is the key hardware.

• Journal of Elementary Mathematics Education in Korea
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• v.22 no.4
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• pp.385-403
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• 2018

Fraction division can be categorized as partitive division, measurement division, and the inverse of a Cartesian product. In the contexts of quotitive division and the inverse of a Cartesian product, the multiply-by-the-reciprocal algorithm is drawn well out. In this study, I analyze the potential and significance of the method of using $1{\div}$(divisor) as an alternative way of developing the multiply-by-the-reciprocal algorithm in the context of quotitive division. The method of using $1{\div}$(divisor) in quotitive division has the following advantages. First, by this method we can draw the multiply-by-the-reciprocal algorithm keeping connection with the context of quotitive division. Second, as in other contexts, this method focuses on the multiplicative relationship between the divisor and 1. Third, as in other contexts, this method investigates the multiplicative relationship between the divisor and 1 by two kinds of reasoning that use either ${\frac{1}{the\;denominator\;of\;the\;divisor}}$ or the numerator of the divisor as a stepping stone. These advantages indicates the potential of this method in understanding the multiply-by-the-reciprocal algorithm as the common structure of fraction division. This method is based on the dual meaning of a fraction as a quantity and the composition of times which the current elementary mathematics textbook does not focus on. It is necessary to pay attention to how to form this basis when developing teaching materials for fraction division.

• Communications of Mathematical Education
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• v.24 no.2
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• pp.345-363
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• 2010

The purpose of this study is to investigate and analyze informal knowledge of students who do not learn the conception of proportion and to identify how the informal knowledge can be used for teaching the conception of proportion in order to present an effective method of teaching the conception. For doing this, proportion was classified into direct and inverse proportion, and 'What are the informal knowledge of students?' were researched. The subjects of this study were 117 sixth-graders who did not have prior learning on direct and inverse proportion. A total eleven problems including seven for direct proportion and four for inverse proportion, all of them related to daily life. The result are as follows; Even though students didn't learn about proportion, they solve the problems of proportion using informal knowledge such as multiplicative reasoning, proportion reasoning, single-unit strategy etc. This result implies mathematics education emphasizes student's informal knowledge for improving their mathematical ability.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.2 s.308
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• pp.52-62
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• 2006

In a fuzzy control system to process fuzzy data in high-speed for intelligent systems, one of the important problems is the improvement of the execution speed in the fuzzy inference and defuzzification stages. Especially, it is more important to have high-speed operations in the consequent part and defuzzification stage. Therefore, in this paper, to improve the speedup of the fuzzy controllers for intelligent systems, we propose an integer line mapping algorithm using only integer addition to convert [0,1] real values in the fuzzy membership functions in the consequent part to integer grid pixels $(400{\times}30)$. This paper also shows a novel defuzzification algorithm without multiplications. Also we apply the proposed system to the truck backer-upper control system. As a result, this system shows a real-time very high speed fuzzy control as compared as the conventional methods. This system will be applied to the real-time high-speed intelligent systems such as robot arm control.

• Journal of The Korean Association For Science Education
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• v.34 no.4
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• pp.335-347
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• 2014

Size/scale is a central idea in the science curriculum, providing explanations for various phenomena. However, few studies have been conducted to explore student understanding of this concept and to suggest instructional approaches in scientific contexts. In contrast, there have been more studies in mathematics, regarding the use of number lines to relate the nature of numbers to operation and representation of magnitude. In order to better understand variations in student conceptions of size/scale in scientific contexts and explain learning difficulties including alternative conceptions, this study suggests an approach that links mathematics with the analysis of student conceptions of size/scale, i.e. the analysis of mathematical structure and reasoning for a number line. In addition, data ranging from high school to college students facilitate the interpretation of conceptual complexity in terms of mathematical development of a number line. In this sense, findings from this study better explain the following by mathematical reasoning: (1) varied student conceptions, (2) key aspects of each conception, and (3) potential cognitive dimensions interpreting the size/scale concepts. Results of this study help us to understand the troublesomeness of learning size/scale and provide a direction for developing curriculum and instruction for better understanding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.