• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.53-58
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• 2008

This paper designs sigma-delta D/A Converter with a high resolution and low power consumption. It reorganizes the input data along LJ, RJ, I2S mode and bit mode to the output data of A/D converter. The D/A converter decodes the original analog signal through HBF, Hold and 5th CIFB(Cascaded Integrators with distributed Feedback as well as distributed input coupling) sigma-delta modulation blocks. It uses repeatedly the addition operation in instead of the multiply operation for the chip area and the performance. Also, the half band filters of similar architecture composed the one block and it used the sample-hold block instead of the sinc filter. We supposed simple D/A Converter decreased in area. The filters of the block analyzed using the matlab tool. The top block designed using the top-down method by verilog language. The designed block is fabricated using Samsung 0.35um CMOS standard cell library. The chip area is 1500*1500um.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.53-61
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• 2004

In this paper, we proposed a new architecture of MAC(Multiplier-Accumulator) to operate high-speed multiplication-accumulation. We used the MBA(Modified radix-4 Booth Algorithm) which is based on the 1's complement number system, and CSA(Carry Save Adder) for addition of the partial products. During the addition of the partial product, the signed numbers with the 1's complement type after Booth encoding are converted in the 2's complement signed number in the CSA tree. Since 2-bit CLA(Carry Look-ahead Adder) was used in adding the lower bits of the partial product, the input bit width of the final adder and whole delay of the critical path were reduced. The proposed MAC was applied into the DWT(Discrete Wavelet Transform) filtering operation for JPEG2000, and it showed the possibility for the practical application. Finally we identified the improved performance according to the comparison with the previous architecture in the aspect of hardware resource and delay.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.864-875
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• 2012

In this paper, we propose a carrier frequency offset estimation method for single-carrier MIMO systems. In the proposed method, phase rotated PN (Pseudo-Noise) sequences are transmitted to prevent a cancelling out of partial PN sequences. After removing a modulation of received PN sequences by multiplying of complex conjugated PN Sequences which are locally generated in receiver, a CFO (Carrier Frequency Offset) is accurately estimated by employing L&R method which is a kind of ML (Maximum Likelihood) estimation algorithm and uses multiple auto-correlatos. In addition, the frequency offset estimation scheme by using channel state information is proposed for accurate CFO estimation in time-varying Rayleigh channel. By performing computer simulations, MSE (Mean Square Error) performance of proposed method is almost same as MSE performance of SISO systems in AWGN channel. Moreover, MSE Performance of proposed method with using channel information is higher than MSE performances of SISO system and conventional method in time-varying Rayleigh channel.

• Journal of the Korean School Mathematics Society
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• v.19 no.1
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• pp.1-19
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• 2016

This study investigated the mathematical notation used today in terms of skip ping the parenthesis. At first we have studied the elementary and secondary curriculum content related to omitted rules. As a result, it is difficult to find explicit evidence to answer that question 'What is the calculation of the $48{\div}2(9+3)$?'. In order to inquire the notation fundamentally, we checked the characteristics on prefix, infix and postfix, and looked into the advantages and disadvantages on infix. At the same time we illuminated the development of mathematical notation from the point of view of skipping the parenthesis. From this investigation, we could check that this interpretation was smooth in the point of view that skipping the parentheses are the image of the function. Through this we proposed some teaching methods including 'teaching mathematical notation based on historic genetic principle', 'reproduction of efforts to overcome the disadvantages of infix and understand the context to choose infix', 'finding the omitted parentheses to identify the fundamental formula' and 'specifying the viewpoint that skipping the multiplication notation can be considered as an image of the function'.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1062-1070
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• 2002

In this paper, variable radix-two multibit coding algorithm is presented and applied in the implementation of discrete cosine transform(DCT) and inverse discrete cosine transform(IDCT). Variable radix-two multibit coding means the 2k SD (signed digit) representation of overlapped multibit scanning with variable shift method. SD represented by 2k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. This paper introduces the suggested algorithm, it's proof and the implementation of DCT/IDCT The implemented IDCT chip with 8 PEs(Processing Elements) and one transpose memory runs at a tate of 400 Mpixels/sec at 54MHz frequency for high speed parallel signal processing, and it's verified in HDTV and MPEG decoder.

• School Mathematics
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• v.9 no.1
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• pp.99-117
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• 2007

In this paper it is discussed how children develop their logical reasoning beyond difficulties in the process of making sense of division with decimals in the classroom setting. When we consider the gap between mathematics at elementary and secondary levels, and given the logical nature of mathematics at the latter levels, it can be seen as important that the aspects of children's logical development in the upper grades in elementary school should be clarified. This study focuses on the teaching and learning of division with decimals in a 5th grade classroom, because it is well known to be difficult for children to understand the meaning of division with decimals. It is suggested that children begin to conceive division as the relationship between the equivalent expressions at the hypothetical-deductive level detached from the concrete one, and that children's explanation based on a reversibility of reciprocity are effective in overcoming the difficulties related to division with decimals. It enables children to conceive multiplication and division as a system of operations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.976-987
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• 1998

In this paper, the effect of nonllinear distortion, caused by a high-power amplifier(HPA) in an orthogonal frequency division multiplexing (OFDM) system, on the receiver part is analyzed. Since the HPA, which can be modeled by a memeoryless Volterra system, distorts OFDM signals in a nonlinear fashion, the received signal at each subchannel includes the multiplicative distortion of 1-st order as well as additive nonlinear distortion of high-order. the nonlinear distortion can be viewed as a nonlinear interchannel interference (NICI) since it consists of harmonic distortions and intermodulation distortions, produced by oother subchannels affecting the subchannel of interest. In this paper, we analytically derive the variance of NICI in terms of average input power using the volterra model for HPA, and then calculate the bit-effor rate(BER) performance of an OFDM system. Also, we propose a simple method to compensate for the phase distortion in OFDM system amplified by HPA, OFDM system employing 16-QAM constellation input.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• The KIPS Transactions:PartC
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• v.15C no.2
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• pp.133-140
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• 2008

In this paper, we propose a high performance elliptic curve cryptographic processor over $GF(2^{163})$. The proposed architecture is based on a modified Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for $GF(2^{163})$ field arithmetic. To achieve a high throughput rates, we design two new word-level arithmetic units over $GF(2^{163})$ and derive a parallelized elliptic curve point doubling and point addition algorithm with uniform addressing based on the Lopez-Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143MHz. Our design is roughly 4.8 times faster with 2 times increased hardware complexity compared with the previous hardware implementation proposed by Shu. et. al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1581-1591
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• 2004

In this paper, we investigate the design of three low-complexity joint estimation algorithms(LJEAs) for frequency offset and carrier phase. The proposed LJEAs are based on the interpolation technique of correlation values of the received signal in frequency and phase domains. With these algorithms, the estimation ranges $\Delta$f$_{d}$${\times}$T$_{s}$ . are less than 1/2N$_{s}$ , and 1/N$_{s}$ which are comparable to conventional algorithms. The Proposed LJEAs require only 2N$_{s}$ or 4N$_{s}$ complex multiplications which are very simple compared with the conventional algorithms. Nevertheless the estimation accuracies of the LJEAs are as good as those of the conventional algorithms. Suitable areas of application include joint estimation of frequency offset and carrier phase in burst-mode digital transmission such as satellite communications.