• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.5
• /
• pp.15-24
• /
• 2009

This paper proposes an effective low power BIST architecture using the pattern mapping method for 100% fault coverage and the transition freezing method for making high correlative low power patterns. When frozen patterns are applied to a circuit, it begins to find a great number of faults at first. However, patterns have limitations of achieving 100% fault coverage due to random pattern resistant faults. In this paper, those faults are covered by the pattern mapping method using the patterns generated by an ATPG and the useless patterns among frozen patterns. Throughout the scheme, we have reduced an amount of applied patterns and test time compared with the transition freezing method, which leads to low power dissipation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.5
• /
• pp.81-90
• /
• 2004

This paper presents new testability measure based on learning, which can be useful in the deterministic process of test pattern generation algorithms. This testability measure uses the structural information that are obtained by teaming. The proposed testability measure searches for test pattern that can early detect the conflict in case of the hardest decision problems. On the other hand in case of the easiest decision problem, it searches for test pattern that likely results in the least conflict. The proposed testability measure reduces CPU time to generate test pattern that accomplishes the same fault coverage as that of the distance-based measure.

• Proceedings of the Korean Information Science Society Conference
• /
• 2000.10c
• /
• pp.30-32
• /
• 2000

본 논문에서는 RTL 회로의 데이터패스에 대한 테스트 용이도 분석방식과 테스트 용이화 설계방식을 제안한다. 데이터패스에 대한 테스트 용이도 분석은 콘트롤러에 대한 정보없이 RTL 회로의 데이터패스만으로 수행한다. 본 논문에서 제안한 테스팅을 고려한 설계방식은 내장된 자체 테스트(BIST)나 주사(scan)방식이 아니며, 주사 방식을 적용했을 때에 비해 본 논문에서 제안한 테스트 용이화 설계방식을 적용했을 때에 보다 적은 면적 증가율(area overhead)을 보인다는 것을 실험을 통해 확인하였다. 또한, 회로 합성 후 ATPG를 통해 적은 면적 증가만으로 높은 고장 검출율(fault coverage)을 얻을 수 있음을 보인다.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.2
• /
• pp.99-107
• /
• 2003

This paper proposes a design for testability (DFT) and testability analysis method for register-transfer level (RTL) circuits. The proposed method executes testability analysis - controllability and observability - on the RTL circuit and determines the insertion points to enhance the testability. Then with the associated priority based on the testability, we insert only a few of the test multiplexers resulting in minimized area overhead. Experimental results shows a higher fault coverage and a shorter test generation time than the scan method. Also, the proposed method takes a shorter test application time required.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.12A
• /
• pp.2008-2014
• /
• 1999

IDDQ testing is an effective testing method to detect various physical defects occurred in CMOS circuits. In this paper, we consider intra-gate shorts within circuit under test and implement IDDQ test pattern generator to find test patterns which detect considered defects. In order to generate test patterns, gate test vectors which detect all intra-gate shorts have to be found by type of gates. Random test sets of 10,000 patterns are applied to circuit under test. If an applied pattern generates a required test vector of any gate, the pattern is saved as an available test pattern. When applied patterns generate all test vectors of all gats or 10,000 patterns are applied to circuit under test, procedure of test pattern generation is terminated. Experimental results for ISCAS'85 bench mark circuits show that its efficiency is more enhanced than that obtained by previously proposed methods.

• 전기의세계
• /
• v.44 no.9
• /
• pp.3-8
• /
• 1995

본 논문에서는 적은 데이타나 censored 데이타도 비교적 유용하게 활용하여 기기의 신뢰도 계산을 할 수 있는 방법을 소개하였다. 이러한 방법은 기기의 테스트를 따로 시스템운전과 분리하여 수행하기 어렵거나 또는 여러개의 시험표본을 준비하기 어려운 경우, 또 기기들의 고장이 그다지 잦지 않아 충분한 고장데이타의 수집이 어려운 경우등에 적용하기 편리하며 발전소나 전력계통은 이러한 경우의 좋은 예가 될 수 있다고 생각한다. 또한 본 방법은 기기들 뿐만이 아니라 각종 측정계기류들의 신뢰도 계산에도 광범위하게 적용할 수 있다. 특히 suspended item들을 신뢰도 계산에 기여시킬 수 있기 때문에 실제로 운전을 해가면서도 끊임없이 기기들의 운전데이타를 수집하고 이들의 신뢰도를 update해 나갈 수 있다. 따라서 본 신뢰도 계산방법은 각종 고장진단 전문가 시스템 개발시 그러한 전문가 시스템들이 보다 상세하고 고장복귀에 실질적인 도움을 줄 수 있는 진단결과를 제시할 수 있도록 지식 베이스를 보강하는데 이용할 수 있을 것이다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.4A
• /
• pp.328-335
• /
• 2005

bIn this paper, built-in self-repair(BISR) is proposed for semiconductor memories. BISR is consisted of BIST(Buit-in self-test) and BIRU(Built-In Remapping Uint). BIST circuits are required not oがy to detect the presence of faults but also to specify their locations for repair. The memory rows are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. According to the experimental result, we can verify algorithm for replacement of faulty cell.

• Journal of Advanced Navigation Technology
• /
• v.15 no.1
• /
• pp.18-24
• /
• 2011

This paper proposes fault diagnosis system which is able to diagnose the fault from present operating condition by analyzing monitored signals with present ship monitoring system without additional sensors. For this all kinds of ship's engine room monitored data are classified with combustion subsystem, heat exchange subsystem and electric motor and pump subsystem by analyzing ship's operation data. To extract dynamic characteristics of these subsystems, log book data of container ship of H shipping company are used.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.6
• /
• pp.78-84
• /
• 1984

We propose a new algorithm which detects stuck-open faults in CMOS circuits without being affected by time skews not using additional circuits. That is, the Domino CMOS circuit structure is used as circuit configurations and the clocking gate in this circuit is modeled as one branch, then test sequence is generated by using the transition test. Also, it is verified by applying this algorithm implemented in VAX II/780 to arbitrary CMOS circuits that all of stuck-open faults which were not detected because of time skews in conventional methods is detected.

• Journal of the Korea Convergence Society
• /
• v.11 no.11
• /
• pp.47-53
• /
• 2020

There is a need for a system that provides early warning of presence and type of failure of automobile wheel bearings through the application of predictive fault analysis technologies. In this paper, we presented a sensor module mounted on a wheel bearing and a diagnostic system that collects, stores and analyzes vehicle acceleration information and vibration information from the sensor module. The developed sensor module and predictive analysis system was tested and evaluated thorough excitation test equipment and real automotive vehicle to prove the effectiveness.