1 |
Rubin A. Parekhji, 'Testing embedded cores and SOCs-DFT, ATPG and BIST solutions,' Proceedings of the 16th International Conference on VLSI Design, pp. 17, 4-8 Jan. 2003
DOI
|
2 |
H. Data and T. Hosokawa, 'A SoC test strategy based on a non-scan DFT method,' Proceedings of the 11 th Asian Test Symposium, pp.305-310, 18-20 Nov. 2002
DOI
|
3 |
J. Hirase, 'Test pattern length required to reach the desired fault coverage,' Proceedings of the 12th Asian Test Symposium, pp.508, 16-19 Nov. 2003
DOI
|
4 |
M. H. Schulz and E. Trischler, 'SOCRATES: A Highly Efficient Automatic Test Pattern Generation System', IEEE Trans. on Computer-Aided Design, Vol.7, no.1, pp.126-137, Jan. 1988
DOI
ScienceOn
|
5 |
W. kunz and D. K. Pradhan, 'Accelerated Dynamic learning for Test Pattern Generation in Combinational Circuits,' IEEE Trans. on Computer-Aided Design, Vol.12, no.5, pp.684-694, May. 1993
DOI
ScienceOn
|
6 |
H. Fujiwara and T. Shimono, 'On the Acceleration of Test Generation Algorithms,' IEEE Trans. on Computer-Aided Design, Vol.C-30, pp. 215-222, 1983
|
7 |
Z. Jiang and S. K. Gupta, 'A test generation approach for systems-on-chip that use intel lectual property cores,' Proceedings of the 12th Asian Test Symposium, pp.278-281, 16-19 Nov. 2003
DOI
|
8 |
Miron Abromovico and Melvin A. Breuer, 'Digital Systems Testing and Testable Design,' IEEE Press, 1990
|