• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.828-830
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• 2003

AVR은 동기발전기의 출력전압을 부하변동에 관계없이 일정하게 제어하며 발전기 및 시스템 보호를 위한 각 종 제어 알고리즘을 구비하고 있다. 종래의 아나로그타입 AVR은 제어설정이 불편하고 제어신뢰성이 떨어지기 때문에 점차 디지털 타입으로 교체되고 있다. 본 연구는 선박발전기에 적용하기 위한 디지털 AVR 개발에 관한 것이다. TI사의 TMS320LF2407 CPU를 사용하여 제어 H/W를 개발했으며, 과여자/저여자제어, Droop제어, 무부하/역률제어 등 다양한 제어기능을 S/W로 구비하여 부하에 따른 적용의 유연성을 높였다. 그리고 전력회로는 IGBT를 사용하여 고속 스위칭 제어함으로써 SCR 방식에 비해 제어 속응성을 개선하였다. 개발 된 제품은 AVR, 직류전원공급장치 및 부하나 계통의 사고시 보호를 위한 전류부스트(CBS)기능을 포함하고 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.567-574
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• 2015

In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.79-85
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• 2004

In this paper, the RF-ID system for ubiquitous tagging applications has been designed, fabricated and analysed. The RF-ID System consists of passive RF-ID Tag and Reader. The passive RF-ID tag consists of rectifier using zero-bias schottky diode which converts RF power into DC power, ID chip, ASK modulator using bipolar transistor and slot loop antenna. We suggest an ASK undulation method using a bipolar transistor to compensate the disadvantage of the conventional PIN diode, which needs large current Also, the slot loop antenna with wider bandwidth than that of the conventional patch antenna is suggested The RF-ID reader consist of patch array antenna, Tx/Rx part and ASK demodulator. We have designed the RF-ID System using EM and circuit simulation tools. According to the measured results, The power level of modulation signal at 1 m from passive RF-ID Tag is -46.76 dBm and frequency of it is 57.2 KHz. The transmitting power of RF-ID reader was 500 mW

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.312-320
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• 2003

This work describes an 8b 200 MHz 0.18 urn CMOS analog-to-digital converter (ADC) based on a pipelined architecture for flat panel display applications. The proposed ABC employs an improved bootstrapping technique to obtain wider input bandwidth than the sampling tate of 200 MHz. The bootstrapuing technique improves the accuracy of the input sample-and-hold amplifier (SHA) and the fast fourier transform (FFT) analysis of the SHA outputs shows the 7.2 effective number of bits with an input sinusoidal wave frequency of 500 MHz and the sampling clock of 200 MHz at a 1.7 V supply voltage. Merged-capacitor switching (MCS) technique increases the sampling rate of the ADC by reducing the number of capacitors required in conventional ADC's by 50 % and minimizes chip area simultaneously. The simulated ADC in a 0.18 um n-well single-poly quad-metal CMOS technology shows an 8b resolution and a 73 mW power dissipation at a 200 MHz sampling clock and a 1.7 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.118-125
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• 2006

A new error amplifier is presented for fast transient response of DC-DC converters. The amplifier has low quiescent current to achieve high power conversion efficiency, but it can supply sufficient current during large signal operation. Two comparators detect large-signal variations, and turn on extra current supplier if necessary. The amount of extra current is well controlled, so that the system stability can be guaranteed in various operating conditions. The simulation results show that the new error amplifier achieves significant improvement in transient response than the conventional one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.31-40
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• 2009

This paper presents a design of a high performance DC-DC boost converter as a power module for SOC designs. It applied to this chip that reduced inductor and capacitor for integrating on a chip, and it operates with a switching frequency of 100MHz. It has reliability and stability in high switching frequency. The controller of DC-DC boost converter is designed by voltage-mode control method and compensated properly. The designed DC-DC converter is fabricated with the 0.18${\mu}m$ standard CMOS technology with a thick-gate oxide option. The overall die size is 8.14$mm^2$, and controller size is 1.15$mm^2$. The converter has the maximum efficiency over 76% for the output voltage of 4V and load current larger 300mA. The load regulation is 0.012% (0.5mV) for the load current change of 100mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.133-142
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• 2004

Recently, the growth of Internet and a variety of multimedia services through Internet increasingly demands high-speed packet transmission, the new routing function, and QoS guarantee on conventional routers. Thus, a new switching mechanical called the MPLS(Multi-Protocol Label Switching), was proposed by IETF(Internet Engineering Task Force) as a solution to meet these demands. In addition the deployment of MPLS network supporting Differentiated Services is required. In this paper, we propose the architecture of the MPLS switch supporting Differentiated Services in the MPLS-based network. The traffic conditioner consists of a classifier, a meter, and a marker. The VOQ-PHB module, which combines input Queue with each PHB queue, is implemented to utilize the resources efficiently. It employs the Priority-iSLIP scheduling algorithm to support high-speed switching. We have designed and verified the new and fast hardware architecture of VOQ-PHB and the traffic conditioner for QoS and high-speed switching using NS-2 simulator. In addition, the proposed architecture is modeled in VHDL, synthesized and verified by the VSS analyzer from SYNOPSYS. Finally, to justify the validity of the hardware architecture, the proposed architecture is placed and routed using Apollo tool.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.277-286
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• 2000

Switch-based network is suitable for the environment of demanding high performance network. Traditional shared-medium Local Area Networks(LANs) do not provide sufficient throughput and latency. Specially, communication performance is more important with multimedia application. In these environments, switch-based network results in high performance. A kind of switch-based network provides higher bandwidth and low latency. Thus high-speed switch is essential to build switch-based LANs. An effective switch design is the most important factor of the switch-based network performance, and is required for the multicast message processing. In the previous cut-through switching technique, switch element reconfiguration has the capability of multicasting and deadlock-free. However, it has problems of low throughput as well as large scale of switch. Therfore, effective multicating can be implemented by using divided hardware unicast and multicast. The objective of this thesis is to suggest switch configuration with these features.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.6 s.324
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• pp.17-24
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• 2004

This paper proposes an efficient technique to protect e-mail server from DDoS attack using the CBQ (Class Based Queuing) algorithm The proposed method classifies incoming trafic to an e-mail server into three classes: 'more important mail traffic', 'less important traffic' and 'unknown traffic' and assigns bandwidths differently to the traffics. By differentiating the bandwidths of classes, normal mail traffic may flow even under DDoS attack in the proposed technique. The proposed technique is implemented on an embedded system which hires a switching processor with the WFHBD(Weighted Fair Hashed Bandwidth Distribution) engine that has been known as an efficient algorithm to distribute a given bandwidth to multiple sources, and it is verified that it can be an efficient way to protect e-mail server from DDoS attack.