• Title/Summary/Keyword: 게이트 시뮬레이션 모델

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A Study on the IoT Network Traffic Shaping Scheme (IoT 네트워크의 트래픽 쉐이핑 기법 연구)

  • Changwon Choi
    • Journal of Internet of Things and Convergence
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    • v.9 no.6
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    • pp.75-81
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    • 2023
  • This study propose the traffic shaping scheme on IoT Network. The proposed scheme can be operated on the gateway which called sink node and control the IoT traffic with considering the traffic type(real-time based or non real-time based). It is proved that the proposed scheme shows a efficient and compatible result by the numerical analysis and the simulation on the proposed model. And the efficient of the proposed scheme by the numerical analysis has a approximate result of the simulation.

Modeling of DFIG based Variable-Speed Pumped Storage Hydro (DFIG 기반의 가변속 양수발전 시스템 모델링)

  • Liu, Zhenqian;An, Hyunsung;Cha, Hanju
    • Proceedings of the KIPE Conference
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    • 2018.11a
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    • pp.15-17
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    • 2018
  • 본 논문은 DFIG기반의 가변속 양수발전소의 조속기, 터빈-수압관(penstock), 발전기/컨버터 및 시스템 제어기를 모델링하였으며, 발전기/컨버터 모델은 하나의 전류원과 임피던스로 등가화 되었다. 최적 운전 조건을 위한 터빈의 속도와 게이트 위치 지령치는 시스템 제어기를 통해서 얻을 수 있으며, 계통 전력의 지령치를 통해서 발전기/컨버터 모델의 전류 지령치를 만들며. 터빈 회전속도와 게이트 위치는 DFIG의 속도와 지령 속도의 비교를 통해 출력된다. 시뮬레이션 모델링을 통해 전력의 지령치 변화에 따라 계통의 전력과 터빈의 응답성을 확인하였다.

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Subthreshold Characteristics of Poly-Si Thin-Film Transistors Fabricated by Using High-Temperature Process (고온공정으로 제작된 다결정실리콘 박막 트랜지스터의 서브트레시홀드 특성)

  • 송윤호;남기수
    • Journal of the Korean Vacuum Society
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    • v.4 no.3
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    • pp.313-318
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    • 1995
  • 비정질실리콘의 고상결정화 및 다결정실리콘의 열상화를 포함한 고온공정으로 제작한 다결정실리콘 박막 트랜지스터의 서브트레시홀드 특성을 연구하였다. 제작된 소자의 전계효과이동도는 60$ extrm{cm}^2$/V.s 이상, 서브트레시홀드 수윙은 0.65 V/decade 이하로 전기적 특성이 매우 우수하다. 그러나, 소자의 문턱전압이 음게이트전압으로 크게 치우쳐 있으며 n-채널과 p-채널 소자간의 서브트레시홀드 특성이 크게 다르다. 열성장된 게이트 산화막을 가진 다결정실리콘 박막 트랜지스터의 서브트레시홀드 특성을 다결정실리콘 활성층내의 트랩과, 게이트산화막과 다결정실리콘 사이의 계면 고정전하를 이용하여 모델링하였다. 시뮬레이션을 통하여 제안된 다결정실리콘의 트랩모델이 실험결과를 잘 설명할 수 있음을 확인하였다.

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Gate Sizing Of Multiple-paths Circuit (다중 논리경로 회로의 게이트 크기 결정 방법)

  • Lee, Seungho;Chang, Jongkwon
    • KIPS Transactions on Computer and Communication Systems
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    • v.2 no.3
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    • pp.103-110
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    • 2013
  • Logical Effort [1, 2] is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. The method of overcoming the shortcomings is shown in [3], but it is constrained for a single logical path. This paper presents an advanced gate sizing method in multiple logical paths based on the equal delay model. According to the results of the simulation, the power dissipation for both the existing logical effort method and proposed method is almost equal. However, compared with the existing logical effort method, it is about 52 (%) more efficient in space.

State Transition Model-based Design of Wireless Gateway Types to Connect between a Sub-network of Things and Mobile Internet and their Performance Evaluations (사물 서브 망과 모바일 인터넷을 연계하는 무선 게이트웨이 타입들의 상태천이모델 기반 설계와 성능 평가)

  • Seong, Cheol-Je;Kim, Changhwa
    • Journal of the Korea Society for Simulation
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    • v.25 no.3
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    • pp.1-14
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    • 2016
  • This paper proposes four general wireless gateway types, which are distinguished by their own processing ways to connect between a wireless sub-network of things and the mobile internet that links mobile network to internet step by step. In this paper, we also design general processing procedures of these four types using the state transition model. Gateways of each types were developed on the basis of the resulted state transition models and their performances were evaluated through several tests, analyzed, and compared each other. As the results of our evaluation, compared with the other types, the type, which combines both of a low-power Sleep-interrupt way and polling ways for receiving data or responses in all the waiting states of a gateway, shows the best performance in all of data transmission real-timeliness, data loss and energy consumption.

Hardware Implementation of Context Modeler in HEVC CABAC Decoder (HEVC CABAC 복호기의 문맥 모델러 설계)

  • Kim, Sohyun;Kim, Doohwan;Lee, Seongsoo
    • Journal of IKEEE
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    • v.21 no.3
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    • pp.280-283
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    • 2017
  • HEVC (high efficiency video coding) exploits CABAC (context-based adaptive binary arithmetic coding) for entropy coding, where a context model estimates the probability for each syntax element. In this paper, a context modeler was designed and implemented for CABAC decoding. lookup table was used to reduce computation and to increase speed. 12 simulations for HEVC standard test sequences and encoder configurations were performed, and the context modeler was verified to perform correction operations. The designed context modeler was synthesized in 0.18um technology. Maximum frequency, maximum throughput, and gate count are 200 MHz, 200 Mbin/s, and 29,268 gates, respectively.

Analysis of Series Resonant High Frequency Inverter using Sequential Gate Control Strategy (순차식 게이트 구동방식에 의한 직렬 공진형 고주파 인버터 특성 해석)

  • 배영호;서기영;권순걸;이현우
    • The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.7 no.3
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    • pp.57-66
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    • 1993
  • This research proposes a high frequency series resonant inverter consisting of equivalent half - bridge model in combination with two L-C linked full-bridge inverter circuits using MOSFET. As a output power control strategy, the sequential gate control method is applied. Also, analysis of operating MODE and state equation is described. From the computer simulation results, the inverters and devices can be shared properly voltage and current rating of the system in accordance with series and parallel operations. And it is confirmed that the proposed system has very stable performance.

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Extraction and Analysis of Dual Gate FET Noise Parameter for High Frequency Modeling (고주파모델링을 위한 이중게이트 FET의 열잡음 파라미터 추출과 분석)

  • Kim, Gue-Chol
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.11
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    • pp.1633-1640
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    • 2013
  • In this paper, noise parameters for high frequency modeling of dual-gate FET are extracted and analyzed. To extract thermal noise parameter of dual gate, noise characteristics are measured by changing input impedance of noise source using Tuner, and the influence of pad parasitic elements are subtracted using open and short dummy structure. Measured results indicated that the dual-gate FET is improved the noise figure by 0.2dB compared with conventional cascode structure FET at 5GHz, and it confirmed that the noise figure has dropped due to reduction of capacitances between the drain and source, gate and drain by simulation and analysis of small-signal parameters.

A QoS Improved MAC Protocol for UWASN with Multi-Gateway (다수의 게이트웨이를 갖는 수중 센서네트워크환경에서 QoS향상을 위한 MAC 프로토콜)

  • Lee, Dong-Won;Kim, Sun-Myeng
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.250-253
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    • 2010
  • Underwater sensor network has attracted more and more attention from the networking research community recently. Most of traditional studies focus on the topology with a single gateway. Underwater sensor network consists of a variable number of sensors and multi-gateway to ensure the reliability of the network. In this paper, we propose a new MAC protocol that can reduce collisions among sensor nodes and improve QoS(Quality of Service) for underwater sensor network with multi-gateway. We evaluate the performance of the proposed scheme through simulation. Simulation results show that the proposed scheme outperforms the existing MAC protocol.

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Gate Oxide Thickness Dependent Threshold Voltage Characteristics for FinFET (FinFET의 게이트산화막 두께에 따른 문턱전압특성)

  • Han, Jihyung;Jung, Hakkee;Lee, Jaehyung;Jeong, Dongsoo;Lee, Jongin;Kwon, Ohshin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.10a
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    • pp.907-909
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    • 2009
  • In this paper, the dependence of threshold voltage on the gate oxide thickness, which it mostly influenced on short channel effects in fabrication of FinFET, has been investigated. The transport model based on three dimensional Possion's equation has been used to analyze influence on gate oxide thickness. The gate oxide thickness is the most important factor to influence on the threshold voltage in nano structure FinFET. The potential distributions of this model are compared with those of three dimensional numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with hree dimensional numerical model, the threshold voltage characteristics have been considered according to the gate oxide thickness of FinFET.

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