• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.17-19
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• 2004

트렌치 게이트 구조를 통해 순방향 전압 강하 손실 없이 기생 사이리스터 래치-업을 억제시키는 새로운 수평형 절연 게이트 바이폴라 트랜지스터 (LIGBT)를 제안하였다. 제안된 소자의 베이스 션트 저항은 정공의 우회로 인하여 감소하였으며, 이에 따라 기생 사이리스터 래치-업이 억제되었다. 제안된 소자의 순방향 전압강하는 트렌치 구조에 의한 유효 채널 폭 증가로 감소하였다. 제안된 소자의 동작 원리 분석을 위해 ISE-TCAD를 이용한 3차원 시뮬레이션을 수행하였으며, 표준 CMOS 공정을 이용하여 소자를 제작 및 측정하였다. 제안된 소자의 순방향 전압 강하는 기존의 LIGBT에 비해 증가하지 않았으며, 래치-업 용량은 2배로 향상되었다. 제안된 소자의 포화 전류는 감소하였으며, 이로 인하여 소자의 강인성 (ruggedness)이 향상되었다.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.459-460
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• 2015

본 논문에서는 2개의 MOSFET으로 구성된 Half-bridge 회로를 구동할 때, 각 MOSFET의 기생성분을 고려하여 게이트 신호를 분석한다. 특히 MOSFET 구동시 게이트 전압에 따른 구간별 등가회로를 구성, 각 구간에서 다른 MOSFET에 상호적으로 미치는 영향을 수식적으로 분석하고, 시뮬레이션을 통해 스위칭 특성을 검증한다.

• Journal of the Korean Vacuum Society
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• v.4 no.3
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• pp.313-318
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• 1995

비정질실리콘의 고상결정화 및 다결정실리콘의 열상화를 포함한 고온공정으로 제작한 다결정실리콘 박막 트랜지스터의 서브트레시홀드 특성을 연구하였다. 제작된 소자의 전계효과이동도는 60$ extrm{cm}^2$/V.s 이상, 서브트레시홀드 수윙은 0.65 V/decade 이하로 전기적 특성이 매우 우수하다. 그러나, 소자의 문턱전압이 음게이트전압으로 크게 치우쳐 있으며 n-채널과 p-채널 소자간의 서브트레시홀드 특성이 크게 다르다. 열성장된 게이트 산화막을 가진 다결정실리콘 박막 트랜지스터의 서브트레시홀드 특성을 다결정실리콘 활성층내의 트랩과, 게이트산화막과 다결정실리콘 사이의 계면 고정전하를 이용하여 모델링하였다. 시뮬레이션을 통하여 제안된 다결정실리콘의 트랩모델이 실험결과를 잘 설명할 수 있음을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.1-6
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• 2010

We present simulation results on DC characteristics of AlGaN/GaN HEMT having stair-type gate electrodes, in comparison with those of the conventional single gate AlGaN/GaN HEMTs and field-plate enhanced AlGaN/GaN HEMTs. In order to reduce the internal electric field near the gate electrode of conventional HEMT and thereby to increase their DC characteristics, we applied three-layered stacking electrode schemes to the standard AlGaN/GaN HEMT structure. As a result, we found that the internal electric field was decreased by 70% at the same drain bias condition and the transconductance (gm) was improved by 11.4% for the proposed stair-type gate AlGaN/GaN HEMT, compared with those of the conventional single gate and field-plate enhanced AlGaN/GaN HEMTs.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.7
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• pp.4411-4417
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• 2015

The proper design of the gate location for injection molding of plastic goods is obtained from three-dimensional injection molding analysis for various design alternatives. This paper is study on effect of gate location in injection molding. It have a decisive impact on productivity and quality of plastic goods. This objectives of this paper is to analysis effect of hot runner gate location for resin filling, weld line, injection pressure to manufacture of automobile air cleaner upper case with injection molding machine. Thus, to analysis these problems in this paper, location of gate are gave variety in 4 CASEs. In this paper, the CAE simulation considering each variations in location of gate is performed to predict the cause of faulty which appears in the injection molding process.

• The KIPS Transactions:PartC
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• v.13C no.5 s.108
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• pp.621-626
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• 2006

A mobile ad hoc network (MANET) is an infrastructureless network that supports multi-hop communication. For the MANET nodes wishing to communicate with nodes in the wired Internet, the global Internet connectivity is required and this functionality can be achieved with the help of the Internet gateway. For the support of reliability and flexibility, multiple Internet gateways can be provisioned for a MANET. In this case, load-balancing becomes one of the important issues since the network performance such as the network throughput can be improved if the loads of the gateways are well-balanced. In this paper, we categorize the load-balancing mechanisms and propose a new metric for load-balancing. Simulation results show that our proposed mechanism using the hop distance and the number of routing table entries as a load-balancing metric enhances the overall network throughput.

• Journal of the Korean Vacuum Society
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• v.20 no.5
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• pp.345-355
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• 2011

GaAs-based metamorphic high electron mobility transistors (MHEMTs) and InP-based high electron mobility transistors (HEMTs) have good microwave and millimeter-wave frequency performance with lower minimum noise figure. MHEMTs have some advantages, especially for cost, compared with InP-based ones. In this paper, InAlAs/InxGa1-xAs/GaAs MHEMTs are simulated for DC/RF small-signal analysis. The hydrodynamic simulation parameters are calibrated to a fabricated 0.1-${\mu}m$ ${\Gamma}$-gate MHEMT device having the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ heterostructure on the GaAs substrate, and the simulations for RF small-signal characteristics are performed, compared with the measured data, and analyzed for the devices. In addition, the simulations for the DC/RF characteristics of the MHEMTs with different gate-recess structures are performed, compared and analyzed.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.3
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• pp.57-66
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• 1993

This research proposes a high frequency series resonant inverter consisting of equivalent half - bridge model in combination with two L-C linked full-bridge inverter circuits using MOSFET. As a output power control strategy, the sequential gate control method is applied. Also, analysis of operating MODE and state equation is described. From the computer simulation results, the inverters and devices can be shared properly voltage and current rating of the system in accordance with series and parallel operations. And it is confirmed that the proposed system has very stable performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.1-5
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• 2011

In this paper, we optimize the gate field plate structure to improve breakdown characteristics of AlGaN/GaN HEMT by two-dimensional device simulator. We have simulated using three parameters such as field-plate length, types of insulator, and insulator thickness and thereby we checked change of the electric field distribution and breakdown voltage characteristics. As optimizing field-plate structure, electric fields concentrated near the gate edge and field-plate edge are effectively dispersed. Therefore, avalanche effect is decresed, so breakdown voltage characteristic is increased. As a result breakdown characteristics of optimized gate field-plate structure are increased by about 300% compared to those of the standard structure.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.30-38
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• 2003

UDP library of Verilog HDL has been used for simulation of digital systems. But it takes a lot of time and efforts to generate a gate-level library equivalent to the UDP library manually due to the characteristic of UDP that does not support synthesis. It is indispensable to generate equivalent gate-level model in testing the digital systems because fault coverage can be reduced without the equivalent gate-level models. So, it is needed to automate the process of generating the equivalent gate-level models. An algorithm to solve this problem has been proposed, but it is unnecessarily complex and time-consuming. This paper suggests a new improved algorithm to implement the conversion to gate-level models, which exploits the characteristic of UDP Experimental results are demonstrated to show the effectiveness of the new algorithm.