• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.876-884
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• 2017

The current-voltage characteristics of Silicon(Si), Germanum(Ge), and hetero tunnel field-effect transistors(TFETs) with source-overlapped gate structure was investigated using TCAD simulations in terms of tunneling. A Si-TFET with gate oxide material $SiO_2$ showed the hump effects in which line and point tunneling appear simultaneously, but one with gate oxide material $HfO_2$ showed only the line tunneling due to decreasing threshold voltage and it shows better performance than one with gate oxide material $SiO_2$. Tunneling mechanism of Ge and hetero-TFETs with gate oxide material of both $SiO_2$ and $HfO_2$ are dominated by point tunneling, and showed higher leakage currents, and Si-TFET shows better performance than Ge and hetero-TFETs in terms of SS. These simulation results of Si, Ge, and hetero-TFETs with source-overlapped gate structure can give the guideline for optimal TFET structures with non-silicon channel materials.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.141-148
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• 2004

Recently, the demand of broadband communications such as high-speed internet, HDTV, 3D-HDTV and ATM backbone network has been increased drastically. For transmitting the broad-bandwidth data using wireless network, it is needed to use ka-band frequency. However, the use of this ka-band frequency is seriously affected to the received data performance by rain fading and atmospheric propagation loss at the Ka-band satellite communication link. So, we need adaptive MODEM to endure the degraded performance by channel environment. In this paper, we will present the structure and design of the 155Mbps adaptive Modem adaptively compensated against channel environment. In order to compensate the rain attenuation over the ka-band wireless channel link, the adaptive coding schemes with variable coding rates and the multiple modulation schemes such as trellis coded 8-PSK, QPSK, and BPSK are adopted. And the blind demodulation scheme is proposed to demodulate without Information of modulation mode at the multi-mode demodulator, and the fast phase ambiguity resolving scheme is proposed. The design and simulation results of adaptive Modem by SPW model are provided. This 155Mbps adaptive MODEM was designed and implemented by single ASIC chip with the $0.25\mu{m}$ CMOS standard cell technology and 950 thousand gates.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.5
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• pp.571-577
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• 2012

In this study, a small movable batch treatment system for dredging soil deposited in a rain water tube is proposed; further, a vacuum silo sorting separation device with a vacuum silo, first-stage sorting separator, and conveyor is designed. The vacuum silo sorting separation device also consists of a storage tank, transferring screw, vacuum gate, screen bar, screen bar cleaner, and vacuum discharging device. In view of the fact that the flow of drawn air in the storage tank is a major factor influencing the sorting separation performance, the optimum shape of the tank is determined by CFD flow analysis. In addition, by using CAE structure analysis, the safety of a storage tank made of boards is examined. The specifications of the vacuum silo sorting separation device are determined by conducting mechanical and dynamic simulations of the driving mechanism of the vacuum silo sorting separation device through 3D-CAD modeling. Following this study, we will design a drum-screen-type second sorter, a decanter-type dehydration device, and waste water tank and pump as a secondary device. Further, on the basis of this design, we will construct a prototype model and carry out a field test.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.713-716
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• 2013

The device performances of N-channel Tunneling FET have been characterized with different intrinsic length between drain and gate($L_{in}$), drain and source doping, permittivity and oxide thickness when the total effective channel length is constant. N-channel Tunneling FET of SOI structure have been used in characterization. $L_{in}$ was from 30nm to 70nm, dose concentration of drain and source were from $2{\times}10^{12}cm^{-2}$ to $2{\times}10^{15}cm^{-2}$ and from $1{\times}10^{14}cm^{-2}$ to $3{\times}10^{15}cm^{-2}$, permittivity was from 3.9 to 29, and oxide thickness was from 3nm to 9nm. The device performances were characterized by Subthreshold slope(S-slope), On/off ratio, and leakage current. From the simulation results, the leakage current have been reduced for long $L_{in}$ and low drain doping. S-slope have been reduced for high source doping, high permittivity and thin oxide thickness. With considering the leakage current and S-slope, it is desirable that are long $L_{in}$, low drain doping, high source doping, high permittivity and thin oxide thickness to optimize device performance in n-channel Tunneling FET.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.5
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• pp.1-6
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• 2007

In wireless mesh networks (WMNs), the end-to-end throughput of a flow decreases drastically according to the traversed number of hops due to interference among different hops of the same flow in addition to interference between hops of different flows with different paths. This paper proposes a distributed multi-channel assignment scheme based on hops (DMASH) to improve the performance of a static WMN. The proposed DMASH is a novel distributed multi-channel assignment scheme based on hops to enhance the end-to-end throughput by reducing interference between channels when transmitting packets in the IEEE 802.11 based multi-interface environments. The DMASH assigns a channel group to each hop, which has no interference between adjacent hops from a gateway in channel assignment phase, then each node selects its channel randomly among the channel group. Since the DMASH is a distributed scheme with unmanaged and auto-configuration of channel assignment, it has a less overhead and implementation complexity in algorithm than centralized multi-channel assignment schemes. Simulation results using the NS-2 showed that the DMASH could improve remarkably the total network throughput in multi-hop environments, comparing with a random channel assignment scheme.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.4
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• pp.33-41
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• 2006

RSA cryptosystem is of great use in systems such as IC card, mobile system, WPKI, electronic cash, SET, SSL and so on. RSA is performed through modular exponentiation. It is well known that the Montgomery multiplier is efficient in general. The critical path delay of the Montgomery multiplier depends on an addition of three operands, the problem that is taken over carry-propagation makes big influence at an efficiency of Montgomery Multiplier. Recently, the use of the Carry Save Adder(CSA) which has no carry propagation has worked McIvor et al. proposed a couple of Montgomery multiplication for an ideal exponentiation, the one and the other are made of 3 steps and 2 steps of CSA respectively. The latter one is more efficient than the first one in terms of the time complexity. In this paper, for faster operation than the latter one we use binary signed-digit(SD) number system which has no carry-propagation. We propose a new redundant binary adder(RBA) that performs the addition between two binary SD numbers and apply to Montgomery multiplier. Instead of the binary SD addition rule using in existing RBAs, we propose a new addition rule. And, we construct and simulate to the proposed adder using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is faster by a minimum 12.46% in terms of the time complexity than McIvor's 2 method and existing RBAs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.94-101
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• 1989

Transport properties of 2DEG at AlGaAs/GaAs interface such as average electron energy, flight distance, each valley occupancy ratio, average electron velocity for various fields are investigated by MONTE-CARLO method. As the electric field increases, more electrons transit drastically from (000) valley to (000) upper valley. This phenomenon shows the nonstationary effect such as velocity overshoot. The duration of the transient decreases from about 1.4 psec for electric field E = 7KV/cm to about 0.7 psec for 12KV/cm. The average electron velocity during transient transport in 2DEG is about 8 times the steady-state velocity for E = 12KV/cm at room temperature. In comparison with bulk GaAs the peak velocity in the 2DEG is higher than that in even pure bulk GaAs at electric field E = 7 KV/cm. On the basis of the fact that the electrons in the 2DEG have larger peak velocity and shorter transient time of velocity than those in the bulk GaAs, it is suggested that the device with 2DEG may obtain higher mobility than that with bulk GaAs.