• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.82-85
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• 2003

MEMS(Micro Electro Mechanical Systems) 응용 분야에 있어서 RF나 Optic등에 응용되는 금속 구조물이나 배선을 위한 도금, 두꺼운 구조물의 식각등을 위해서 수십 um두께의 감광막이 필요하다. 특히 이러한 감광막은 도금을 위한 전단계에서 몰드 형성에 이용되는데 그 이유는 제작이 용이할 뿐만 아니라 다양한 두께 형성이 가능하고 금속과의 선택적 제거가 쉬운 장점이 있다. 감광막 몰드가 갖추어야 할 조건으로는 수직에 가까운 측면 기울기, 두께, 도금액에 대찬 저항성을 들 수 있으며 그 중에서 측면 기울기 개선에 관한 연구가 많이 진행되고 있다. 본 논문에서는 감광막의 형상에 영향을 주는 요인을 찾아내고 수식모델링을 통해 측면 기울기를 예측하고자 한다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.168-172
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• 2005

본 연구에서는 평판 디스플레이 Photo공정 중에서 무회전 도포(Spinless Coating)방식으로 기판(Glass)에 감광제 약액을 도포한 후 용매(Solvent)를 제거시키기 위한 진공건조장치(Vacuum dryer)에서 감광제 도포막의 품질에 영향을 주지 않는 범위 안에서의 용매 제거시간을 단축하기 위한 진공챔버의 용적에 따른 진공포트의 크기 및 배치에 대한 최적화를 구현하였다. 구현된 챔버의 용적과 진공포트의 크기 및 배치를 바탕으로 진공건조장치를 챔버, 챔버 구동부, 기판 구동부, 진공펌프, 그리고 $N_2$ 공급부로 모듈화하여 구성하였으며. 실제 도포 기판을 이용하여 진공건조를 실시한 후 도포막을 검사함으로써 진공포트에 대한 최적화를 검증함과 동시에 진공건조 능력을 확인하였다.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.2
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• pp.7-12
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• 1998

감광성 BCB를 사용한 MCM-D기판에 신뢰성있는 비아형성을 위하여 BCB의 공정 특성과 C2F6를 사용한 플라즈마 cleaning 영향을 분석하였다. 절연막, 금속배선재료로 각각 감광성 BCB, Cu를 사용하여 MCM-D 기판을 제작 분석한 결과 BCB는 soft bake 후 초기 두께의 50%정도 두께 손실이 있었으며 해상도는 15um이었다. BCB층에 비아 형성후 C2F6 가스로 플라즈마 cleaning 하고 AES로 비아표면을 분석한 결과 유기물 C는 검출되지 않은 반면 플라즈마 cleaning을 하지 않은 비아를 분석한 결과 유기물 성분의 C가 많이 검출되었 고 Ar 스퍼터에 의해서도 완전히 제거되지 않았다. 따라서 감광성 BCB를 절연막으로 사용 한 MCM-D 기판 제작공정에서 비아 형성후 C2F6를 이용한 플라즈마 cleaning의 필요성을 확인하였다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.12
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• pp.591-596
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• 2006

we have been developed on the ultra high concentration ozone generator system which is the core technology in the realization of the semiconductor photoresist strip process using the ozone-vapor chemistry. The proposed ozone generator system has the structure of the surface discharge type which adopt the high purity ceramic dielectric tube. We investigate the performance of the proposed ozone generator system experimentally and the results show that the system has very high ozone concentration characteristics of $19.7[wt%/O_2]$ at the flow rate of $0.3[{\ell}/min]$ of each discharge cell. As a result of the silicon wafer photoresist strip test, we obtained the strip rate of about 400[nm/min] at the ozone concentration of $16[wt%/O_2]$ and flow rate of $8[{\ell}/min]$. So, we confirmed that it's possible to use the proposed high concentration ozone generator system for the ozone-vapor photoresist strip process in the semiconductor and FPD industry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.22-23
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• 2006

A process for removal of photoresist(PR) m semiconductor manufacturing using water vapor with ozone is presented. For the realization of the ozone/vapor mixture process, high concentration ozone generator and process facilities have developed. As a result of the silicon wafer PR strip test, we confirmed the high efficiency PR strip rates of 400nm/mm or more at the ozone concentration of 16wt%/$O_2$. The ozone/vapor mixture process is more effective than the ozonized water Immersion process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.11
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• pp.1143-1148
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• 2004

In this study, photoresist stripping in semiconductor or LCD (liquid crystal display) fabrication processes using DIO, was investigated. In order to obtain the high PR stripping efficiency of DIO. we have developed new ozone-generating system with high ozone concentration and ozone-resolving system with high contact ratio. In this study, we obtained ozone gas concentrations of 11 % by new ozone-generating system, ozone-resolving efficiency of 99.5 % and maximum solubility of 130 ppm in deionized water. We applied the newly designed equipments to photoresist stripping processes and obtained similar results to SPM(sulfuric-peroxide mixture) process characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.11
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• pp.977-982
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• 2007

The realization of the photoresist(PR) removal method with vaporized water and ozone gas mixture has been studied for the LCD TFT array manufacturing. The developed PR stripper uses the water boundary layer control method based on the high concentration ozone production technology. We develop the prototype of PR stripper and experiment to find the optimal process parameter condition like as the ozone gas flow/concentration, process reaction time and thin boundary layer formation. As a results, we realize the LCD PR strip rate over the 0.4 ${\mu}m/min$ and this PR removal rate is more than 5 times higher than the conventional immersion type ozonized water process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.5
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• pp.353-357
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• 2010

Recently, silicon etching have received much attention for display industry, nano imprint technology, silicon photonics, and MEMS application. After the etching process, removing of etch mask and residue of sidewall is very important. The investigation of the etched mask removing was carried out by using the ashing, HF dipping and acid cleaning process. Experiment shows that oxygen component of reactive gas and photoresist react with silicon and converting them into the mask fence. It is very difficult to remove by using ashing or acid cleaning process because mask fence consisted of Si and O compounds. However, dilute HF dipping is very effective process for SiOx layer removing. Finally, we found optimized condition for etched mask removing.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.1
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• pp.37-44
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• 2015

In this paper, we have investigated a selective assembly method of single-walled carbon nanotubes (SWCNTs) on a silicon substrate using only photolithographic process and then proposed a fabrication method of field effect transistors (FETs) using SWCNT-based patterns. The aminopropylethoxysilane (APTES) patterns, which are formed for positively charged surface molecular patterns, are utilized to assemble and align millions of SWCNTs and we can more effectively assemble on a silicon (Si) surface using this method than assembly processes using only the 1-octadecyltrichlorosilane (OTS). We investigated a selective assembly method of SWCNTs on a Si surface using surface-programmed APTES and OTS patterns and then a fabrication method of FETs. photoresist(PR) patterns were made using photolithographic process on the silicon dioxide (SiO2) grown Si substrate and the substrate was placed in the OTS solution (1:500 v/v in anhydrous hexane) to cover the bare SiO2 regions. After removing the PR, the substrate was placed in APTES solution to backfill the remaining SiO2 area. This surface-programmed substrate was placed into a SWCNT solution dispersed in dichlorobenzene. SWCNTs were attracted toward the positively charged molecular regions, and aligned along the APTES patterns. On the contrary, SWCNT were not assembled on the OTS patterns. In this process, positively charged surface molecular patterns are utilized to direct the assembly of negatively charged SWCNT on SiO2. As a result, the selectively assembled SWCNT channels can be obtained between two electrodes(source and drain electrodes). Finally, we can successfully fabricate SWCNT-based multi-channel FETs by using our self-assembled monolayer method.

• Clean Technology
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• v.29 no.4
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• pp.255-261
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• 2023

Power semiconductors are semiconductors used for power conversion, transformation, distribution, and control. Recently, the global demand for high-voltage power semiconductors is increasing across various industrial fields, and optimization research on high-voltage IGBT components is urgently needed in these industries. For high-voltage IGBT development, setting the resistance value of the wafer and optimizing key unit processes are major variables in the electrical characteristics of the finished chip. Furthermore, the securing process and optimization of the technology to support high breakdown voltage is also important. Etching is a process of transferring the pattern of the mask circuit in the photolithography process to the wafer and removing unnecessary parts at the bottom of the photoresist film. Ion implantation is a process of injecting impurities along with thermal diffusion technology into the wafer substrate during the semiconductor manufacturing process. This process helps achieve a certain conductivity. In this study, dry etching and wet etching were controlled during field ring etching, which is an important process for forming a ring structure that supports the 3.3 kV breakdown voltage of IGBT, in order to analyze four conditions and form a stable body junction depth to secure the breakdown voltage. The field ring ion implantation process was optimized based on the TEG design by dividing it into four conditions. The wet etching 1-step method was advantageous in terms of process and work efficiency, and the ring pattern ion implantation conditions showed a doping concentration of 9.0E13 and an energy of 120 keV. The p-ion implantation conditions were optimized at a doping concentration of 6.5E13 and an energy of 80 keV, and the p+ ion implantation conditions were optimized at a doping concentration of 3.0E15 and an energy of 160 keV.