• 제어로봇시스템학회논문지
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• 제22권7호
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• pp.513-518
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• 2016

The piezoelectric actuating device is known for its large power density and simple structure. It can generate a larger force than a conventional actuator and has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need an analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with an analog part and need digital-to-analog converters, which makes the system bulky compared with the small size of piezoelectric devices. To overcome these weaknesses, we are developing a single-chip controller that can handle analog and digital signals simultaneously using mixed-signal FPGA technology. This gives more flexibility than traditional fixed-function microcontrollers, and the control speed can be increased greatly due to the parallel processing characteristics of the FPGA. In this paper, we developed a floating-point multiplier, PWM generator, 80-kHz power control loop, and 1-kHz position feedback control loop using a single mixed-signal FPGA. It takes only 50 ns for single floating-point multiplication. The PWM generator gives two outputs to control the charging and discharging of the high-voltage output capacitor. Through experimentation and simulation, it is demonstrated that the designed control loops work properly in a real environment.

• 산업경영시스템학회지
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• 제37권1호
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• pp.165-171
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• 2014

We develop an optimization algorithm for a periodic review inventory system under a stochastic budget constraint. While most conventional studies on the periodic review inventory system consider a simple budget limit in terms of the inventory investment being less than a fixed budget, this study adopts more realistic assumption in that purchasing costs are paid at the time an order is arrived. Therefore, probability is employed to express the budget constraint. That is, the probability of total inventory investment to be less than budget must be greater than a certain value assuming that purchasing costs are paid at the time an order is arrived. We express the budget constraint in terms of the Lagrange multiplier and suggest a numerical method to obtain optional values of the cycle time and the safety factor to the system. We also perform the sensitivity analysis in order to investigate the dependence of important quantities on the budget constraint. We find that, as the amount of budget increases, the cycle time and the average inventory level increase, whereas the Lagrange multiplier decreases. In addition, as budget increases, the safety factor increases and reaches to a certain level. In particular, we derive the condition for the maximum safety factor.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1880-1885
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• 1989

In this paper, a new approach for systolic array realizing the discrete cosine transform (DCT) based on discrete Fourier transform (DFT) of an input sequence is presented. The proposed array is based on a simple modified DFT(MDFT) version of the Goertzel algorithm combined with Kung's approach and is proved perfectly. This array requires N cells, one multiplier and takes N clock cycles to produce a complete N-point DCT and also is able to process a continuous stream of data sequences. We have analyzed the output signal-to-noise ratio(SNR) and designed the circuit level layout of one-PE chip. The array coefficients are static adn thus stored-product ROM's can be used in place of multipliers to limit cost as eliminate errors due to coefficients quantization.

• 한국전산유체공학회지
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• 제14권4호
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• pp.101-108
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• 2009

We present a new finite-element scheme for direct numerical simulation of particle suspensions in simple shear flow of a viscoelastic fluid in 3D. The sliding tri-periodic representative cell concept has been combined with DEVSS/DG finite element scheme by introducing constraint equations along the domain boundary. Rigid body motion of the freely suspended particle is described by the rigid-shell description and implemented by Lagrangian multipliers on particle boundaries. We present the bulk rheology of suspensions through the numerical examples of single-, two- and many-particle problems, which represent a large number of such systems in simple shear flow. We report the steady bulk viscosity and the first normal stress coefficient, which show shear-thickening behavior for both properties.

• 전자공학회논문지A
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• 제30A권3호
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1012-1015
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. The adjust parameter of PID to achieve best response of process which be using time and may be error if user are not expert. Nowadays this problem was solved by develop PID controller which can analysis and auto tune parameter are appropriate with process which used principle of Ziegler ? Nichols but it are expensive and designed for each task. Thus, this paper proposes auto tune PID based on FPGA by use principle of Dahlin which maximum overshoot not over 5 percentages and do not fine tuning again. It have performance in control process are neighboring controller in industrial and simple to use. Especially, It can use various process and low price. The auto tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. It was verified by control model of temperature control system.

• 정보처리학회논문지A
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• 제11A권2호
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• pp.115-122
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• 2004

본 논문에서는 전류모드 CMOS를 사용하여 다치 가산기 및 다치 승산기를 구현하였으며, 먼저 효과적인 집적회로 설계 이용성을 갖는 전류모드 CMOS를 사용하여 3치 T-게이트와 4치 T-게이트를 구현하였다. 구현된 다치 T-게이트를 조합하여 유한체 $GF(3^2)$의 2변수 3치 가산표와 승산표를 실현하는 회로를 구현하였으며, 이들 다치 T-게이트를 사용하여 유한체 $GF(4^2)$의 2변수 4치 가산표와 승산표를 실현하는 회로를 구현하였다. 또한, Spice 시뮬레이션을 통하여 이 회로들에 대한 동자특성을 보였다. 다치 가산기 및 승산기들은 $1.5\mutextrm{m}$ CMOS 표준 기술의 MOSFET 모델 LEVEL 3을 사용하였고, 단위전류는 $15\mutextrm{A}$로 하였으며, 전원전압은 3.3V를 사용하였다. 본 논문에서 구현한 전류모드 CMOS의 3치 가산기와 승산기, 4치 가산기와 승산기는 일정한 회선경로 선택의 규칙성, 간단성, 셀 배열에 의한 모듈성의 이점을 가지며 특히 차수 m이 증가하는 유한체의 두 다항식의 가산 및 승산에서 확장성을 가지므로 VLSI화 실현에 적합한 것으로 생각된다.

• Korea-Australia Rheology Journal
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• 제18권4호
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• pp.171-181
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• 2006

We present a short review for authors' previous work on direct numerical simulations for inertialess hard particle suspensions formulated either with a Newtonian fluid or with viscoelastic polymeric fluids to understand the microstructural evolution and the bulk material behavior. We employ two well-defined bi-periodic domain concepts such that a single cell problem with a small number of particles may represent a large number of repeated structures: one is the sliding bi-periodic frame for simple shear flow and the other is the extensional bi-periodic frame for planar elongational flow. For implicit treatment of hydrodynamic interaction between particle and fluid, we use the finite-element/fictitious-domain method similar to the distributed Lagrangian multiplier (DLM) method together with the rigid ring description. The bi-periodic boundary conditions can be effectively incorportated as constraint equations and implemented by Lagrangian multipliers. The bulk stress can be evaluated by simple boundary integrals of stresslets on the particle boundary in such formulations. Some 2-D example results are presented to show effects of the solid fraction and the particle configuration on the shear and elongational viscosity along with the micro-structural evolution for both particles and fluid. Effects of the fluid elasticity has been also presented.

• 한국통신학회논문지
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• 제28권2A호
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• pp.102-109
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• 2003

본 논문에서는 GF(2m)상의 표준기저를 사용한 새로운 형태의 승산 알고리즘을 제안하였다. 제안된 알고리즘에서 승산의 전개를 데이터 선택방식으로 취하여 연산과정을 단순화하였다. 승산연산의 결과 발생하는 m차 이상의 차수를 갖는 항에 대하여 기약다항식을 적용하여 m-1차 이하의 표준기저들로 나타나게 하였다. 제안된 알고리즘의 회로구현을 위해 멀티플렉서를 사용하여 회로를 구성하였고, GF(24)에 대한 설계의 예를 보였다. 새로운 승산회로는 그 구성이 규칙성을 가지며 m의 증가에 대한 확장이 용이하다. 또한, 타 논문과의 비교결과 사용소자의 수가 비교적 적다. 따라서, VLSI의 실현과 타 연산회로에의 적용에 적합하다 할 수 있다.

• 대한의용생체공학회:의공학회지
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• 제24권2호
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• pp.83-89
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• 2003

기체전자증폭기는 기존의 기체검출기의 표류공간에 위치하여 표류전기장을 매우 짧은 거리에 걸쳐 전자사태가 가능한 세기(〉 $10^4$ V/cm) 이상으로 압축함으로써 기체이득을 향상시키는 개념적으로 간단한 기구이다 이 기구는 양면이 금속(구리)으로 얇게 코팅된 수십 $\mu\textrm{m}$ 두께의 절연성 foil에 화학적 에칭이나 고출력 레이저빔 천공방법을 이용하여 직경 100 $\mu\textrm{m}$ 이하의 미소 hole들을 100-200 $\mu\textrm{m}$ 간격으로 균일하게 뚫어 놓은 구조로 되어 있다. 본 연구에서는 다양한 실험조건에서 기체전자증폭기의 동작특성을 조사하였으며 또한 기체전자증폭기의 섬광특성을 이용하여 표준 CCD 카메라와 결합하여 X-선 영상을 획득함으로써 디지털 X-선 영상센서로서의 가능성을 제시하였다.