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The Design of GF(2m) Parallel Multiplier using data select methodology  

Byun, Gi-Young (인하대학교 전자공학과 회로및시스템 연구실)
Choi, Young-Hee (인하대학교 전자공학과 회로및시스템 연구실)
Kim, Heong-Soo (인하대학교 전자공학과 회로및시스템 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.28, no.2A, 2003 , pp. 102-109 More about this Journal
Abstract
In this paper, the new multiplicative algorithm using standard basis over GF(2m) is proposed. The multiplicative process is simplified by data select method in proposed algorithm. After multiplicative operation, the terms of degree greater than m can be expressed as a polynomial of standard basis with degree less than m by irreducible polynomial. For circuit implementation of proposed algorithm, we design the circuit using multiplexer and show the example over GF(24). The proposed architectures are regular and simple extension for m. Also, the comparison result show that the proposed architecture is more simple than privious multipliers. Therefore, it well suited for VLSI realization and application other operation circuits.
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