• Title/Summary/Keyword: (100) p-type silicon

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Investigation of varied suface passivation layers for solar cells (태양전지를 위한 다양한 표면 패시베이션(passivation) 막들의 연구)

  • Lee, Ji-Youn;Lee, Soo-Hong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.05a
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    • pp.90-93
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    • 2004
  • In this work, we have used different techniques for the surface passivation: conventional thermal oxidation (CTO), rapid thermal oxidation (RTO), and plasma-enhanced chemical vapour deposition (PECVD). The surface passivation qualities of eight different single and combined double layer have been investigated both on the phosphorus non-diffused p-type FZ silicon and on phosphorus diffused emitter of 100 ${\Omega}/Sq$ and 40 ${\Omega}/Sq$. In the single layer, silicon dioxide $(SiO_2)$ passivates good on the emitter while silicon nitride (SiN) passivates better than on the non-diffused surface. In the double layers, CTO/SiN1 passivates very well both on non-diffused surface on the emitter. However, RTO/SiN1 and RTO/SiN2 stacks are more suitable for surface passivation in solar cells caused by a relatively good passivation qualities and the low optical reflection. Applying these stacks in solar cells we achieved 18.5 % and 18.8 % on 0.5 ${\Omega}$ cm FZ-Si with planar and textured front surface, respectively. The excellent open circuit voltage $(V_{oc})$ of 675.6 mV is obtained the planar cell with RTO/SiN stack.

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A study on the Dielectric Properties of IPN based on the Epoxy/Silicon and Epoxy/Urethane (Epoxy/Silicon Epoxy/Urethane계 IPN 복합재료의 개발에 관한 연구)

  • Shin, Joong-Hong;Jung, Eun-Shik;Park, Chung-Hoo
    • Proceedings of the KIEE Conference
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    • 1987.11a
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    • pp.504-507
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    • 1987
  • Interpenerating Polymer Networks (IPNs) are unique type of polymer blend, synthesized by swelling a crossed polymer (Epoxy) with second polymer (Silicon) and also we adopted Urethane as the second polymer. The relationship between dielectric and mechanical properties of high temperature curing IPNs(E/S, E/U) are investigated. The ratios of weight that we formed we re two kind of thing, one (E/S) about 1[wt%]. 3[wt%], 5[wt%], 7[wt%], 10[wt%], and the other (E/U) about 5[wt%], 15[wt%], 25[wt%]. It was heat-cured for 24hours at $100^{\circ}C$ 48 hours at $10^{\circ}C$, 5 hours at $130^{\circ}C$, 15hours at $130^{\circ}C$ in E/S and also for 5 hours at $130^{\circ}C$ in E/U. From the viewpoint of dielectric and mechanical properties, the optimum condition is obtained from the sample cured for 5hours at $130^{\circ}C$ for 1[wt%] in the E/S, and also obtained from the sample cure d for 5 hours at $130^{\circ}C$ in E/U.

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Characterization of $HfO_2 /SiON$ stack structure for gate dielectrics (ALD를 이용한 극박막 $HfO_2 /SiON$ stack structure의 특성 평가)

  • Kim, Youngsoon;Lee, Taeho;Jaemin Oh;Jinho Ahn;Jaehak Jung
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.11a
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    • pp.115-121
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    • 2002
  • In this research we have investigated the characteristics of ultra thin $HfO_2 /SiON$stack structure films using several analytical techniques. SiON layer was thermally grown on standard SCI cleaned silicon wafer at $825^{\circ}C$ for 12sec under $N_2$O ambient. $HfO_2 /SiON$$_4$/$H_2O$ as precursors and $N_2$as a carrier/purge gas. Solid HfCl$_4$was volatilized in a canister kept at $200^{\circ}C$ and carried into the reaction chamber with pure $N_2$carrier gas. $H_2O$ canister was kept at $12^{\circ}C$ and carrier gas was not used. The films were grown on 8-inch (100) p-type Silicon wafer at the $300^{\circ}C$ temperature after standard SCI cleaning, Spectroscopic ellipsometer and TEM were used to investigate the initial growth mechanism, microstructure and thickness. The electrical properties of the film were measured and compared with the physical/chemical properties. The effects of heat treatment was discussed.

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The Electrical and Microstructural Properties of ZnO:N Thin Films Grown in The Mixture of $N_2$ and $O_2$ by RF Magnetron Sputtering

  • Jin, Hu-Jie;Lee, Eun-Cheal;So, Soon-Jin;Park, Choon-Bae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.144-145
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    • 2006
  • ZnO is a promising material to make high efficiency violet or blue light emitting diodes (LEDs) for its large binding energy (60meV) and big bandgap. But the high quality p-type conduction of ZnO is a dilemma to achieve LEDs with it. In present study, we presented a reliable method to prepare ZnO thin films on (100)silicon substrates by RF magnetron sputtering in the mixture ambient of $N_2$ and $O_2$, accompanying with low pressure annealing in the sputtering chamber in $O_2$ at $600^{\circ}C$ and $800^{\circ}C$ respectively. X-ray diffraction and Hail effect with Van der Paul method were performed to test ZnO films. Seeback effect was also carried out to identify carrier types in ZnO films and showed the N-doped ZnO film annealed at $800^{\circ}C$ had achieved p-type conduction.

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Computer simulation for the effects of inserting the textured ZnO and buffer layer in the rear side of ZnO/nip-SiC: H/metal type amorphous silicon solar cells (Zno/nip-SiC:H/금속기판 구조 비정질 실리콘 태양전지의 후면 ZnO 및 완충층 삽입 효과에 대한 컴퓨터 수치해석)

  • Jang, Jae-Hoon;Lim, Koeng-Su
    • Proceedings of the KIEE Conference
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    • 1994.07b
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    • pp.1277-1279
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    • 1994
  • In the structure of ZnO/nip-SiC: H/metal substrate amorphous silicon (a-Si:H) solar cells, the effects of inserting a rear textured ZnO in the p-SiC:H/metal interface and a graded bandgap buffer layer in the i/p-SiC:H have been analysed by computer simulation. The incident light was taken to have an intensity of $100mW/cm^2$(AM-1). The thickness of the a-Si:H n, ${\delta}$-doped a-SiC:H p, and buffer layers was assumed to be $200{\AA},\;66{\AA}$, and $80{\AA}$, respectively. The scattering coefficients of the front and back ZnO were taken to be 0.2 and 0.7, respectively. Inserting the rear buffer layer significantly increases the open circuit voltage($V_{oc}$) due to reduction of the i/p interface recombination rate. The use of textured ZnO markedly improves collection efficiency in the long wavelengths( above ${\sim}550nm$ ) by back scattering and light confinement effects, resulting in dramatic enhancement of the short circuit current density($J_{sc}$). By using the rear buffer and textured ZnO, the i-layer thickness of the ceil for obtaining the maximum efficiency becomes thinner(${\sim}2500{\AA}$). From these results, it is concluded that the use of textured ZnO and buffer layer at the backside of the ceil is very effective for enhancing the conversion efficiency and reducing the degradation of a-Si:H pin-type solar cells.

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Simulation Study of ion-implanted 4H-SiC p-n Diodes (이온주입 공정을 이용한 4H-SiC p-n Diode에 관한 시뮬레이션 연구)

  • Lee, Jae-Sang;Bahng, Wook;Kim, Sang-Cheol;Kim, Nam-Kyun;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.2
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    • pp.128-131
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    • 2009
  • Silicon carbide (SiC) has attracted significant attention for high frequency, high temperature and high power devices due to its superior properties such as the large band gap, high breakdown electric field, high saturation velocity and high thermal conductivity. We performed Al ion implantation processes on n-type 4H-SiC substrate using a SILVACO ATHENA numerical simulator. The ion implantation model used Monte-Carlo method. We simulated the effect of channeling by Al implantation in both 0 off-axis and 8 off-axis n-type 4H-SiC substrate. We have investigated the effect of varying the implantation energies and the corresponding doses on the distribution of Al in 4H-SiC. The controlled implantation energies were 40, 60, 80, 100 and 120 keV and the implantation doses varied from $2{\times}10^{14}$ to $1{\times}10^{15}\;cm^{-2}$. The Al ion distribution was deeper with increasing implantation energy, whereas the doping level increased with increasing dose. The effect of post-implantation annealing on the electrical properties of Al-implanted p-n junction diode were also investigated.

n-type porous silicon formation using Pt mask & its application (Pt를 mask로 이용한 n-type 다공질 실리콘 형성과 응용)

  • Kang, Chul-Goo;Min, Nam-Ki;Lee, Seung-Jae
    • Proceedings of the KIEE Conference
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    • 2000.07c
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    • pp.1760-1762
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    • 2000
  • 본 논문은 기존의 $Si_{3}N_4$, SiN 물질 대신 Pt를 사용해 HF 용액속에서 다공질 실리콘과 전극을 동시에 형성하는 기술을 개발하였다. Pt를 실리콘 웨이퍼 위에 직접 증착한 후 습식 에칭과 Lift-off 공정을 사용하여 Pt를 패터닝하였다. 습식 에칭은 에칭용액의 온도를 일정하게 유지하는 것이 중요하며, 증착한 Pt 박막이 BOE 에칭에 견디고, Lift-off 공정이 가능하기 위해서는 기판온도를 l100$^{\circ}C$ 이하로 해야한다. Pt를 사용하면 기존의 mask에서 발생하는 가장자리 부분에서의 전류 집중이 방지되기 때문에 다공질 실리콘이 일정한 깊이로 형성되고, Al대신 오믹 전극으로 사용할 수 있다. 현재 Pt를 mask와 전극으로 이용한 P-I-N UV detector, 광 바이오센서, 습도센서 제작등에 응용 연구가 진행되고 있다.

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Microfabrication of Submicron-size Hole on the Silicon Substrate using ICP etching

  • Lee, J.W.;Kim, J.W.;Jung, M.Y.;Kim, D.W.;Park, S.S.
    • Proceedings of the Korean Vacuum Society Conference
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    • 1999.07a
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    • pp.79-79
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    • 1999
  • The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.

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Growth of Nanocrystalline Diamond Films on Poly Silicon (폴리 실리콘 위에서 나노결정질 다이아몬드 박막 성장)

  • Kim, Sun Tae;Kang, Chan Hyoung
    • Journal of the Korean institute of surface engineering
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    • v.50 no.5
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    • pp.352-359
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    • 2017
  • The growth of nanocrystalline diamond films on a p-type poly silicon substrate was studied using microwave plasma chemical vapor deposition method. A 6 mm thick poly silicon plate was mirror polished and scratched in an ultrasonic bath containing slurries made of 30 cc ethanol and 1 gram of diamond powders having different sizes between 5 and 200 nm. Upon diamond deposition, the specimen scratched in a slurry with the smallest size of diamond powder exhibited the highest diamond particle density and, in turn, fastest diamond film growth rate. Diamond deposition was carried out applying different DC bias voltages (0, -50, -100, -150, -200 V) to the substrate. In the early stage of diamond deposition up to 2 h, the effect of voltage bias was not prominent probably because the diamond nucleation was retarded by ion bombardment onto the substrate. After 4 h of deposition, the film growth rate increased with the modest bias of -100 V and -150 V. With a bigger bias condition(-200 V), the growth rate decreased possibly due to the excessive ion bombardment on the substrate. The film grown under -150V bias exhibited the lowest contact angle and the highest surface roughness, which implied the most hydrophilic surface among the prepared samples. The film growth rate increased with the apparent activation energy of 21.04 kJ/mol as the deposition temperature increased in the range of $300{\sim}600^{\circ}C$.

Fabrication and Characteristics of High Efficiency Silicon PERL (passivated emitter and rear locally-diffused cell) Solar Cells (PERL (passivated emitter and rear locally-diffused cell) 방식을 이용한 고효율 Si 태양전지의 제작 및 특성)

  • Kwon, Oh-Joon;Jeoung, Hun;Nam, Ki-Hong;Kim, Yeung-Woo;Bae, Seung-Chun;Park, Sung-Keoun;Kwon, Sung-Yeol;Kim, Woo-Hyun;Kim, Ki-Wan
    • Journal of Sensor Science and Technology
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    • v.8 no.3
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    • pp.283-290
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    • 1999
  • The $n^+/p/p^+$ junction PERL solar cell of $0.1{\sim}2{\Omega}{\cdot}cm$ (100) p type silicon wafer was fabricated through the following steps; that is, wafer cutting, inverted pyramidally textured surfaces etching by KOH, phosphorus and boron diffusion, anti-reflection coating, grid formation and contact annealing. At this time, the optical characteristics of device surface and the efficiency of doping concentration for resistivity were investigated. And diffusion depth and doping concentration for n+ doping were simulated by silvaco program. Then their results were compared with measured results. Under the illumination of AM (air mass)1.5, $100\;mW/cm^2$ $I_{sc}$, $V_{oc}$, fill factor and the conversion efficiency were 43mA, 0.6 V, 0.62. and 16% respectively.

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