• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.3
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• pp.128-132
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• 2004

The perovskite ferroelectric materials of the PZT, SBT and BST series will attract much attention for application to ULSI devices. Among these materials, the BST ($Ba_0.6$$Sr_0.4$/$TiO_3$) is widely considered the most promising for use as an insulator in the capacitors of DRAMS beyond 1 Gbit and high density FRAMS. Especially, BST thin films have a good thermal-chemical stability, insulating effect and variety of Phases. However, BST thin films have problems of the aging effect and mismatch between the BST thin film and electrode. Also, due to the high defect density and surface roughness at grain boundarys and in the grains, which degrades the device performances. In order to overcome these weakness, we first applied the chemical mechanical polishing (CMP) process to the polishing of ferroelectric film in order to obtain a good planarity of electrode/ferroelectric film interface. BST ferroelectric film was fabricated by the sol-gel method. And then, we compared the surface characteristics before and after CMP process of BST films. We expect that our results will be useful promise of global planarization for FRAM application in the near future.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.09a
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• pp.5-8
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• 2001

The $Sr_{0.8}Bi_{2.4}Ta_{2}O_{9}(SBT)$ thin films are deposited on Pt-coated electrode$(Pt/TiO_{2}/SiO_{2}/Si)$ using RF magnetron sputtering method. With increasing annealing tempera ture from $600[^{\circ}C]$ to $850[^{\circ}C]$, Bi-layered perovskite phase was crystallized above $650[^{\circ}C]$. The dielectric constant is 213 at annealing temperature of $750[^{\circ}C]$ and dielectric loss have a stable value within 0.1. Leakage current density is $1.01{\times}10^{-8} A/cm^{2}$ at annealing temperature of $750[^{\circ}C]$ The fatigue characteristics of SBT thin films did not change up to $10^{10}$ switching cycles.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1546-1548
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• 2001

The $Sr_{0.8}Bi_{2.4}Ta_2O_9$(SBT) thin films are deposited on Pt-coated electrode(Pt/$TiO_2$/ $SiO_2$/Si) using RF magnetron sputtering method. With increasing annealing temperature from 600[$^{\circ}C$] to 850[$^{\circ}C$], Bi-layered perovskite phase was crystallized above 650[$^{\circ}C$]. The dielectric constant is 213 at annealing temperature of 750[$^{\circ}C$] and dielectric loss have a stable value within 0.1. Leakage current density is $1.01{\times}10^{-8}A/cm^2$ at annealing temperature of 750[$^{\circ}C$].

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.162-162
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• 2012

Sub 100 nm의 Complementary Metal-Oxide-Semiconductor (CMOS) 소자를 구동하기 위해서는 2.0 nm 이하의 $SiO_2$ oxide에 해당하는 전기적 특성이 요구된다. 그러나 2.0 nm 이하의 $SiO_2$에서는 누설 전류가 너무 크기 때문에 이를 대체하기 위해서 유전 상수 (dielectric permittivity)가 높은 $HfO_2$ (${\varepsilon}=25$), $Al_2O_3$, $HfO_2/Al_2O_3$ laminate 등의 high-k dielectric 물질들이 연구되고 있다[1]. High-k dielectric 물질의 전기적 특성은 박막 조성, 두께 및 전극과의 계면에 생성되는 계면 층이나 불순물(Impurity) 거동에 크게 의존하므로 High-k dielectric/전극(Metal or Si) 구조에서 조성 및 불순물의 거동에 대한 정확한 평가가 주요 쟁점으로 부각되고 있다. 이를 평가하기 위해 일반적으로 $Ar^+$ ion에 의한 depth profiling 분석이 진행되나 Oxygen 원자의 선택적 식각에 기인된 분석 깊이 분해능(Depth Resolution) 왜곡으로 계면 층의 형성이나 불순물의 거동을 정확하게 평가할 수 없다. 이러한 예로는 $Ta_2O_5$ 및 $SrBi_2Ta_2O_9$와 같은 다 성분 계 산화막에 $Ar^+$ ion 주사 시 발생하는 선택적인 식각(Preferential Sputtering) 때문에 박막의 실제 조성 및 거동을 평가하는 것은 어렵다고 보고된 바 있다[2,3]. 본 연구에서는 $90{\AA}$인 적층 $Hf_xO_y/Al_xO_y/Hf_xO_y$ 구조에서의 불순물 거동 분석 능력 확보 상 주요 인자인 깊이 분해능 개선을 Secondary Ion Mass Spectroscopy(SIMS)의 primary ion 종, impact energy 및 주사 각도를 변화시켜 ~1 nm 수준까지 구현하였다. 이러한 분석 깊이 분해능의 개선은 Low Impact Energy, 입사 이온의 glancing angle 및 Cluster ion 적용에 의존하며 이들 요인의 효과에 대해 비교/고찰하고자 한다.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.921-923
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• 1999

비휘발성 메모리의 고집적화와 적응학습형 뉴럴 소자의 실현을 위하여 1-트랜지스터 구조 강유전체 비휘발성 메모리(MFS-FET)를 SOI 기판위에 제작하고 평가하였다. 먼저 SBT($Sr_{0.8}Bi_{2.2}Ta_{2}O_{9}$)를 직접 Si위에 증착하고 C-V를 측정하여 1V의 메모리 윈도우를 얻음으로써 비휘발성 메모리로써의 동작가능성을 확인하였다. 또한 다양하게 게이트의 W/L 비를 바꾸어서 MFS-FET를 제작하여 다양한 드레인 전압-드레인 전류 특성을 얻었고 실제로 쓰기와 읽기 동작을 수행하여 MFS-FET가 비휘발성 메모리로써 제대로 동작하고 있음을 확인하였다.

• Journal of the Korean Ceramic Society
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• v.35 no.9
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• pp.945-952
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• 1998

Ferroelectric Sr0.8Bi2.4Ta2O9 stock solutions were prepared by MOD(Metaloganic Decompostion) process. The phase transformation for the layered perovskite of the SBT thin films by changing RTA(Rapid her-mal Annealing) temperatuer from 700$^{\circ}C$to 780$^{\circ}C$ were observed using XRD and SEM. Layered perovskite phase began to appear above 740$^{\circ}C$ and then SBT thin films were annealed at 800$^{\circ}C$ for 1hr for its com-plete crystallization. The specimens showed well shaped hysteresis curves without post annealing that car-ried out after deposition of Pt top electrode. The SBT thin films showed the asymmetric ferroelectric pro-perties. It was confirmed that the properties were caused by interface effect to SBT and electrode by leak-age current density measurement and asymmetric properties reduced by post annealing. At post annealing temperature of 800$^{\circ}C$ remanant polarization values (2Pr) were 6.7 9 ${\mu}$C/cm2 and those of leakage current densities were 3.73${\times}$10-7 1.32${\times}$10-6 A/cm2 at 3, 5V respectively. Also bismuth bonding types of SBT thin film surface were observed by XPS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.668-671
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• 2001

The Sr$\_$0.8/Si$\_$2.4/Ta$_2$O$\_$9/(SBT) thin films are deposited on Pt-coated electrode(Pt/TiO$_2$/SiO$_2$/Si) using RF magnetron sputtering method. With increasing post-annealing temperature from 600[$^{\circ}C$] to 850[$^{\circ}C$], Bi-layered perovskite phase was crystallized above 650[$^{\circ}C$]. The maximum remanent polarization and the coercive electric field is 11.60[${\mu}$C/$\textrm{cm}^2$], 48[kV/cm] respectively. The leakage current density of SBT capacitor at post-annealing temperature of 750[$^{\circ}C$] is 1.01${\times}$10$\^$-8/ A/$\textrm{cm}^2$ at 100[kV/cm]. The fatigue characteristics of SBT thin films did not change up to 10$\^$10/ switching cycles.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1553-1555
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• 1999

Recently, $SrBi_2Ta_2O_9$(SBT) and $Pb(ZrTi)O_3$(PZT) were much attracted as materials of capacitor for ferroelectric random access memory(FRAM) showing higher read/write speed, lower power consumption and nonvolartility. Bi-layered SBT thin film has appeared as the most prominent fatigue free and low operation voltage for use in nonvolatile memory. To highly integrate FRAM, SBT thin film should be etched. A lot of papers on SBT thin film and its characteristics have been studied. However, there are few reports about SBT thin film due to difficulty of etching. In order to investigate properties of etching of SBT thin film, SBT thin film was etched in $CF_4$/Ar gas plasma using magnetically enhanced inductively coupled plasma (MEICP) system. When $CF_4/(CF_4+Ar)$ is 0.1, etch rate of SBT thin film was $3300{\AA}/min$, and etch rate of Pt was $2495{\AA}/min$. Selectivities of SBT to Pt. $SiO_2$ and photoresist(PR) were 1.35, 0.6 and 0.89, respectively. With increasing $CF_4$ gas, etch rate of SBT thin film and $P_t$ decreased.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.141-157
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• 2001

Highly reliable packaged 64kbit ferroelectric memories with $0.8{\;}\mu\textrm{m}$ CMOS ensuring ten-year retention and imprint at 125^{\circ}C$ have been successfully developed. These superior reliabilities have resulted from steady integration schemes free from the degradation, due to layer stress and attacks of process impurities. The resent results of research and development for ferroelectric memories at Hynix Semiconductor Inc. are summarized in this invited paper.

• Transactions on Electrical and Electronic Materials
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• v.1 no.1
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• pp.40-44
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• 2000

Metal-ferroelectric-insulator-semoiconductor field effect transistor (MFISFETs) were fabricated using CMOS processes. The Pt/SBT/NO combined layers were etched for forming a conformal gate by using Ti/Cr metal masks and a two step etching method, By the method, we were able to fabricate a small-sized gate with the dimension of $16/4{\mu}textrm{m}$ in the width/length of gate. It has been chosen the non-self aligned source and drain implantation process, We have deposited inter-layer dielectrics(ILD) by low pressure chemical vapor deposition(LPCVD) at $380^{circ}C$ after etching the gate structure and the threshold voltage of p-channel MFISFETs were about 1.0 and -2.1V, respectively. It was also observed that the current difference between the $I_{ON}$(on current) and $I_{OFF}$(off current) that is very important in sensing margin, is more that 100 times in $I_{D}-V_{G}$ hysteresis curve.