• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.865-870
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• 2003

The MFIS (Metal-Ferroelectric-Insulator-Semiconductor) capacitors were fabricated using a metalorganic decomposition method. Thin layers of CeO$_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the CeO$_2$ layer. The morphology of films and the interface structures of the BLT and the CeO$_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 2.82 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Journal of the Korean Ceramic Society
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• v.36 no.10
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• pp.1087-1093
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• 1999

Bioglass which is one of the surface active bionmaterials has a good biocompatibility but a poor mechanical strength, In the present work therefore two types of fluoride-containing bioglasses were coated on an alumina to improve mechanical strength. Crystallization of the coating layer and the hydroxyapatite formation on the bioactive glass coatings in tris-buffer solution were studied. When bioactive glass coated alumina was heat-treated Na2CaSi3O8 crystal was formed on the layer at lower temperature while wollastonite(CaSIO3) was obtained at higher temperature. Hydroxyapatite forming rate on the coating layer with Na2CaSi3O8 crystal was delayed with SiO2 contents in glass composition. However the hydroxyapatite was developed in 20minutes regardless SiO2 contents when the coating layer crystallized into wollastonite. More amount of P3+ ions were leached out of the coating layer with wollastonite than that with Na2CaSi3O8 crystal while Na+ and Ca2+ ions were leached out more easily from the Na2CaSi3O8 crystal containing coating layer.

• Journal of Ceramic Processing Research
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• v.13 no.spc2
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• pp.336-340
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• 2012

Wide band gap p-type hydrogenated amorphous silicon oxide (a-SiO:H) buffer layer has been used at the interface of transparent conductive oxide (TCO) and hydrogenated amorphous silicon (a-Si:H) p-type layer of a p-i-n type a-Si:H solar cell. Introduction of 5 nm thick buffer layer improves in blue response of the cell along with 0.5% enhancement of photovoltaic conversion efficiency (η). The cells with buffer layer show higher open circuit voltage (Voc), fill factor (FF), short circuit current density (Jsc) and improved blue response with respect to the cell without buffer layer.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1277-1279
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• 1994

In the structure of ZnO/nip-SiC: H/metal substrate amorphous silicon (a-Si:H) solar cells, the effects of inserting a rear textured ZnO in the p-SiC:H/metal interface and a graded bandgap buffer layer in the i/p-SiC:H have been analysed by computer simulation. The incident light was taken to have an intensity of $100mW/cm^2$(AM-1). The thickness of the a-Si:H n, ${\delta}$-doped a-SiC:H p, and buffer layers was assumed to be $200{\AA},\;66{\AA}$, and $80{\AA}$, respectively. The scattering coefficients of the front and back ZnO were taken to be 0.2 and 0.7, respectively. Inserting the rear buffer layer significantly increases the open circuit voltage($V_{oc}$) due to reduction of the i/p interface recombination rate. The use of textured ZnO markedly improves collection efficiency in the long wavelengths( above ${\sim}550nm$ ) by back scattering and light confinement effects, resulting in dramatic enhancement of the short circuit current density($J_{sc}$). By using the rear buffer and textured ZnO, the i-layer thickness of the ceil for obtaining the maximum efficiency becomes thinner(${\sim}2500{\AA}$). From these results, it is concluded that the use of textured ZnO and buffer layer at the backside of the ceil is very effective for enhancing the conversion efficiency and reducing the degradation of a-Si:H pin-type solar cells.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.200-201
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• 2007

The SBT($SrBi_2Ta_2O_9$) thin films with $Bi_2O_3$ buffer layer were deposited on Pt/Ti/$SiO_2$/Si substrate by R.F. magnetron sputtering method in order to improve the ferroelectric characteristics. In SBT thin films, the deficiency of bismuth during the process due to its volatility results in an obvious non stoichiometry of the films and the presence of secondary phases. $Bi_2O_3$ buffer layer was found to be effective to achieve the low temperature crystallization and improve the ferroelectric properties of SBT thin films. Ferroelectric properties and crystallinities of SBT thin films with various post annealing of $Bi_2O_3$ buffer layer were observed as various annealing temperature, using X-Ray Diffraction (XRD), scanning electron microscopy (SEM), Keithley 237 and HP 4192A Impedance Analyzer.

• Journal of the Korean Vacuum Society
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• v.17 no.6
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• pp.560-565
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• 2008

$(Pb_{0.98}La_{0.08})(Zr_{0.65}Ti_{0.35})O_3$ (PLZT) thin films with $TiO_2$ buffer layers were deposited on Pt/Ti/$SiO_2$/Si substrates by an R.F. magnetron sputtering method in order to improve the ferroelectric characteristics of the films. And the ferroelectric properties and crystallinities of the PLZT thin films were investigated in terms of the effects of the post annealing temperatures of $TiO_2$ buffer layers between a platinum bottom electrode and PLZT thin film. The ferroelectric properties of the PLZT thin films improved as increasing of the post annealing temperatures of $TiO_2$ layers, thereby reaching their maximum at $600^{\circ}C$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.151-157
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• 1996

We propose a mechanism for the formation of pinholes in the Si-buffer layer, through the observations with varying the process- and structure variables in the SEPOX (selective poly-oxidation) process, an isolation method for sub-u DRAMs. Pinholes are formed through the accumulation of Si vacancies generated by the oxidation of Si, in which Si atoms leave the sites (vacancies) at the Si/SiO$_{2}$ interfaces and diffuse into the oxide to be oxidized near interface. In the course of the accumulation of Si-vacancies, the stress induced in the Si-buffer layer affects the migration of vacancies to result in the final size and distribution of pinholes. This paper may be, to our knowledge, the first report about the oxidation-induced pinhole in the Si/SiO$_{2}$ system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.186-189
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• 2003

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $ZrO_2$ and $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the $ZrO_2$ and $CeO_2$ layer. AES show no interdiffusion and the formation of amorphous $SiO_2$ layer is suppressed by using the $ZrO_2$ and $CeO_2$ film as buffer layer between the BLT film and Si substrate. The width of the memory window in the C-V curves for the $BLT/ZrO_2/Si$ and $BLT/CeO_2/Si$ structure is 2.94 V and 1.3V, respectively. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Journal of the Korean Ceramic Society
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• v.40 no.2
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• pp.206-211
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• 2003

Effects of substrates and buffer layer upon the formation of crystalline phases and ferroelectricity of $YMnO_3$ thin films were investigated. The hexagonal $YMnO_3$ was easily formed on Si(100) while the mixed phases, hexagonal and orthorhombic $YMnO_3$, on $Pt(111)/TiO_2/SiO_2/Si$ substrate. When the $Y_2O_3$ buffer layer of 70 nm thick was inserted between the substrates and the $YMnO_3,$ the c-axis oriented hexagonal single phase formed on both substrates, Si(100) and $Pt(111)/TiO_2/SiO_2/Si$. The leakage current density of the hexagonal $YMnO_3$ thin films was lower than that consisting of mixed phases, hexagonal and orthorhombic. Furthermore the hexagonal $YMnO_3$ with c-axis preferred orientation showed the lowest leakage current density. The remnant polarization from a P-E hysteresis curve for the $YMnO_3$ formed on Si(100) was 0.14 without buffer layer and $0.24_{mu}C/cm^2$ for that with buffer layer. For the $Pt(111)/TiO_3/SiO_3/Si$ substrates, the specimen without $Y_2O_3$buffer layer did not show the hysteresis curve, while the buffer-layered has the remnant polarization of $1.14_{mu}C/cm^2$. It was concluded that the leakage current density and the ferroelectricity for the $YMnO_3$ thin films could be controlled by varying crystalline phases and their preferred orientation which depend on the kind of substrates and whether the $Y_2O_3$buffer layer exist or not.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.115-120
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• 2007

Polycrystalline silicon (poly-Si) thin film transistors (TFTs) might be fabricated on the mica substrate and transferred to a flexible plastic substrate because mica can be easily cleaved into a thin layer. To overcome the adhesion and stress problem between poly-Si film and mica substrate, a buffer layer consisting of $SiO_x/Ta/Ti$ three layers has been developed. The $SiO_x$ layer is for electrical isolation, the Ti layer is for adhesion of $SiO_{x}$ and mica. and Ta is for stress relief between $SiO_x$ and Ti. A TFT was fabricated on the mica substrate by a conventional Si process and was successfully transferred to a plastic substrate.