• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
• /
• pp.465-465
• /
• 2013

Inorganic 물질인 SiO2 dielectric 위에 organic dielectric PVP (4-vinyphenol)를 spin coating으로 올려, inorganic/organic dielectric 형태의 double layer구조로 High-performance amorphous indiumgallium zinc oxide thin-film transistors (IGZO TFT)를 제작하여 보았다. SiO2 dielectric을 buffer layer로 80 nm, PVP는 10Wt% 400 nm로 구성하였으며, 200 nm single SiO2 dielectric과 동일한 수준의 leakage current 특성을 MIM Capacitor 구조를 통해서 확인할 수 있었다. 이 소자의 장점은 용액공정의 도입으로 공정 시간의 단축 및 원가 절감을 이룰 수 있으며, dielectric과 channel 사이의 균일한 interface의 형성으로 interface trap 개선 및 Yield 향상의 장점을 갖는다. 우리는 실험을 통해서 SiO2 buffer layer가 수직 electric field에 의한 leakage current을 제어하고, PVP dielectric은 interface를 개선하는 것을 확인하였다. Vth의 negative shift 및 slope의 향상으로 구동전압이 줄어들고, 균일한 I-V Curve 형성을 통해서 Process Yield의 향상을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 하계학술대회 논문집
• /
• pp.326-329
• /
• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

• 마이크로전자및패키징학회지
• /
• 제15권4호
• /
• pp.25-29
• /
• 2008

Reliability and performance in metal gate/high-k device with multiple gate dielectrics were investigated. MOSFETs with a thin $HfSiO_x$ layer on a thermal Si02 dielectric as gate dielectrics exhibit excellent mobility and low interface trap density. However, the distribution of threshold voltages of $HfSiO_x/SiO_2$ stack devices were wider than those of $SiO_2$ and $HfSiO_x$ single layer devices due to the penetration of Hf and/or intermixing of $HfSiO_x$ with underlying $SiO_2$. The results of TZDB and SILC characteristics suggested that a certain portion of $HfSiO_x$ layer reacted with the underlying thick $SiO_2$ layer, which in turn affected the reliability characteristics.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 추계학술대회 논문집 전기물성,응용부문
• /
• pp.36-38
• /
• 2005

This study is about how to lower the driving voltage that enables to move the micro droplet by the EWOD (Electro Wetting On Dielectric) mechanism. EWOD is well known that it is used ${\mu}-TAS$ digital micro fluidics system. As the device which is fabricated with dielectric layer between electrode and micro droplet is applied voltage, the hydrophobic surface is changed into the hydrophilic surface by electrical property. Therefore, EWOD induces the movement of micro droplet with reducing contact angle of micro droplet. The driving voltage was depended on the dielectric constant of dielectric layer, thus it can be reduced by increase of dielectric constant. Typically, very high voltage ($100V{\sim}$) is used to move the micro droplet. In previous study, we used $Ta_{2}O_{5}$ as the dielectric layer and driving voltage was 23V that reduced 24 percent compared with $SiO_2$. In this study, we used $BZN(Bi_{2}O_{3}ZnO-Nb_{2}O_{5})$ layer which had high dielectric constant. It was operated the just 12V. And micro droplet was moved within Is on 15V. It was reduced the voltage until 35 percents compare with $Ta_{2}O_{5}$ and 50 percents compare with $SiO_2$. The movement of micro droplet within 1s was achieved with BZN (ferroelectrics)just on 15V.

• E2M - 전기 전자와 첨단 소재
• /
• 제16권9호
• /
• pp.64.2-65
• /
• 2003

A 4 nm layer of ZrOx (targeted x-2) was deposited on an interfacial layer(IL) of native oxide (SiO, t∼1.2 nm) surface on 200 mm Si wafers by a manufacturable atomic layer chemical vapor deposition technique at 30$0^{\circ}C$. Some as-deposited layers were subjected to a post-deposition, rapid thermal annealing at $700^{\circ}C$ for 5 min in flowing oxygen at atmospheric pressure. The experimental x-ray diffraction, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, and high-resolution parallel electron energy loss spectroscopy results showed that a multiphase and heterogeneous structure evolved, which we call the Zr-O/IL/Si stack. The as-deposited Zr-O layer was amorphous $ZrO_2$-rich Zr silicate containing about 15% by volume of embedded $ZrO_2$ nanocrystals, which transformed to a glass nanoceramic (with over 90% by volume of predominantly tetragonal-$ZrO_2$(t-$ZrO_2$) and monoclinic-$ZrO_2$(m-$ZrO_2$) nanocrystals) upon annealing. The formation of disordered amorphous regions within some of the nanocrystals, as well as crystalline regions with defects, probably gave rise to lattice strains and deformations. The interfacial layer (IL) was partitioned into an upper Si $o_2$-rich Zr silicate and the lower $SiO_{x}$. The latter was sub-toichiometric and the average oxidation state increased from Si0.86$^{＋}$ in $SiO_{0.43}$ (as-deposited) to Si1.32$^{＋}$ in $SiO_{0.66}$ (annealed). This high oxygen deficiency in $SiO_{x}$ indicative of the low mobility of oxidizing specie in the Zr-O layer. The stacks were characterized for their dielectric properties in the Pt/{Zr-O/IL}/Si metal oxide-semiconductor capacitor(MOSCAP) configuration. The measured equivalent oxide thickness (EOT) was not consistent with the calculated EOT using a bilayer model of $ZrO_2$ and $SiO_2$, and the capacitance in accumulation (and therefore, EOT and kZr-O) was frequency dispersive, trends well documented in literature. This behavior is qualitatively explained in terms of the multi-layer nanostructure and nanochemistry that evolves.ves.ves.

• 대한전자공학회논문지SD
• /
• 제44권5호
• /
• pp.8-14
• /
• 2007

본 논문에서는 MOS 소자의 게이트 유전체로 사용될 고유전 박막으로 $HfO_2$/Hf 박막을 제조하여 그 전기적 특성을 관찰하였다. $HfO_2$박막은 TEMAH와 $O_3$ 전구체를 사용한 ALD 방법으로 p-type (100) 실리콘 웨이퍼 위에 증착하였다. $HfO_2$막을 증착시키기 전에 중간층으로써 Hf 금속 층을 증착하였다. Round-type의 MOS 커패시터 제작을 위해, 상부 전극은 Al 또는 Pt을 이용하여 약 2000 ${\AA}$ 두께의 전극을 형성하였다. $HfO_2$ 박막은 화학정량적 특성을 보였으며, $HfO_2$/Si 계면에서 Si-O 결합 대신 Hf-Si 결합과 Hf-Si-O 결합이 관찰되었다. $HfO_2$와 Si 사이의 Hf 중간층은 $SiO_x$의 성장이 억제되었고, $HfSi_xO_y$으로 변형되었다. 이러한 결과로 $HfO_2$/Hf/Si 구조에서 Hf 중간층이 있음으로 게이트 유전체의 고유전율이 유지되면서 계면 특성이 개선됨을 확인하였다.

• 한국진공학회지
• /
• 제5권2호
• /
• pp.161-168
• /
• 1996

For the improvement of microelectronic thin film interconnection materials, dielectric passivation effects on the electromigration phenomena were studied. Using Al-1%Si, various shaped patterns were fabricated and dielectric passivation layers of several structures were deposited on the $SiO_2$ layer. Lifetime of straight pattern showed 2~5 times longer than the other patterns that had various line width and area. It is believed that the flux divergence due to the structural inhomogeneity and so the current crowding effects shorten the lifetime of thin film interconnections. The lifetime of thin film interconnections seems to depend on both the passivation materials and the passivation thickness. PSG/$SiO_2$ dielectric passivation layers showed longer lifetime than $Si_3N_4$ dielectric passivation layers. This results from the PSG on $SiO_2$ layer reduces stress and from the improvement of resistance to the moisture and to the mobile ion such as sodium. This is also believed that the lifetime of thin film interconnections seems to depend on the passivation thickness in case of the same deposition materials.

• 전자공학회논문지 IE
• /
• 제43권4호
• /
• pp.8-12
• /
• 2006

본 논문에서는 $SiO_2-ZnO-B_2O_3$ 계 및 $P_2O_5$-ZnO-BaO 계의 반사율과 유전특성을 $TiO_2$의 양에 따라 조사하였다. 반사율은 $TiO_2$ 함량이 증가함에 따랴 감소하였다 여기서 $P_2O_5$-ZnO-BaO계는 $SiO_2-ZnO-B_2O_3$ 계보다 더 낮은 반사율을 나타내었으며, 유전상수는 $P_2O_5$-ZnO-BaO 계가 $SiO_2-ZnO-B_2O_3$ 계보다 높았다. 두 계 모두 유전상수는 $TiO_2$의 양에 따라 증가하는 특성을 보였다. 이 결과는 높은 반사율과 항복특성이 요구되는 PDP디스플레이의 후면 유전층에 적용할 수 있을 것으로 생각된다.

• 한국재료학회지
• /
• 제12권5호
• /
• pp.347-352
• /
• 2002

A transparent dielectric of the $PbO-B_2O_3-SiO_2-A1_2O_3$ system which was a low melting glass has been used for PDP (Plasma Display Panel), but it has a problem which is a reaction to be occurred between a transparent dielectric layer and electrodes (Ag, ITO) after firing. This research was conducted for ion migration of $Ag^+\$ and $Sn^ {2+}$ during firing three different frits of low melting glass. The result showed that yellowing phenomena occurred through a chemical reaction between $Ag^+\$and $Sn^ {2+}$ at 550~58$0^{\circ}C$ for 20~60 min. In addition, it was confirmed that the migration of $Sn^{2+}$ from ITO electrode made a strong effect on the yellowing phenomena.

• 한국전기전자재료학회논문지
• /
• 제25권1호
• /
• pp.24-28
• /
• 2012

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.