• Journal of the Korean Ceramic Society
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• v.41 no.1
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• pp.30-35
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• 2004

PMW-PZT thick films of about $30{\mu}m$ thickness were fabricated on Pt/$TiO_2$/$SiN_x$Si substrate by the hybrid method of screen printing and PZT sol application. With the increase of the number of the sol application times, the sintered density and electrical properties of PMW-PZT thick films were evidently increased. For the PMW-PZT thick film with PZT sol application of 10-times, the dielectric constant ($\varepsilon_r$) was 745 at the frequency of 100 KHz and thepiezoelectric coefficient ($d_33$) was 155 pC/N at the applied pressure of 1 atm.

• Journal of the Korean Vacuum Society
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• v.4 no.2
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• pp.217-223
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• 1995

절연보호막에 따른 AI-1%Si 박막배선의 평균수명(MTF, Mean-Time-to-Failure) 및 electromigration에 대한 저항성, 즉 활성화에너지(Q)변화 등을 측정 비교하였다. 박막배선은 $5000\AA$두께로 열산화막 처리된 p-Si(100)기판위에 $7000\AA$의 AI-1%Si을 증착한 후 photolithography 공정으로 형성시켰다. Electromigration test를 위한 박막배선은 $3\mu$m의 폭과 $400\mu$m, $1600\mu$m의 두 가지 길이를 가지며 절연보호막 효과를 알아보기 위해 그 위에 $3000\AA$의 두께로 SiO2, PSG, Si3N4등 절연보호막을 APCVD 및 PECVD를 이용하여 각각 증착시켰다. 가속화 실험을 위해 인가된 전류밀도는 4.5X106A/cm2이었고 180, 210, $240^{\circ}C$온도에서 d.c. 인가 후의 저항변화를 측정하여 평균수명을 구한 후 Black 방정식을 이용하여 활성화에너지를 측정하였다. AI-1%Si 박막배선에서 electromigration에 대한 활성화에너지값은 $400\mu$m길이의 경우 0.44eV(nonpassivated), 0.45eV(Si3N4 passivated), 0.50 eV(PSG passivated), 그리고 0.66 eV(SiO2 passivated)로 각각 측정되었다. $1600\mu$m 길이의 AI-1%Si 박막배선 실험에서도 같은 절연보호막 효과가 관찰되었다. 따라서 SiO2, PSG, Si3N4등 절연보호막은 AI-1%Si 박막배선에서의 electromigration에 대한 저항력을 높여 결함방지효과를 보이며 수명을 향상시킨다. SiO2의 절연보호막의 경우가 AI-1%Si 박막배선의 electromigration에 대한 가장 강한 저항력을 보이며 평균수명도 높게 나타났다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.599-603
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• 2003

Ferroelectric B $i_4$$_{-x}$N $d_{x}$ $Ti_3$ $O_{12}$ (BNdT) thin films with the composition(x=0.75) were prepared on Pt/Ti/ $SiO_2$(100) substrate by metal-organic deposition. The films were annealed by various temperatures from 550 to $650^{\circ}C$ and then the electrical and structural characteristics of BNdT films were investigated for the application of FRAM. Electrical properties such as dielectric constant, 2Pr and capacitance were quite dependent on the thermal heat treatment. The measured 2Pr value on the BNdT capacitor annealed at $650^{\circ}C$ was 56$\mu$C/$\textrm{cm}^2$ at an applied voltage of 5V. In fatigue characteristics value remained constant up to 8$\times$10$^{10}$ read/write switching cycles at a frequency of 1Mhz regardless of annealing temperatures.

• Journal of Sensor Science and Technology
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• v.16 no.2
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• pp.97-103
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• 2007

Crystallized carbon nitride film that has many stable physical and/or chemical properties has been expected potentially by a new electrical material. However, one of the most significant problems degrading the quality of carbon nitride films is an existence of N-H and C-H bonds from the deposition environment. The possibility of these reactions with hydroxyl group in carbon nitride films, caused by a hydrogen attack, was suggested and proved in our previous reports that this undesired effect could be applied for fabricating micro-humidity sensors. In this study, MIS capacitor and MIM capacitor with $5{\mu}m{\times}5{\mu}m$ meshes were fabricated. As an insulator, carbon nitride film was deposited on a $Si_{3}N_{4}/SiO_{2}/Si$ substrate using reactive magnetron sputtering system, and its dielectric constant, C-V characteristics and humidity sensing properties were investigated. The fabricated humidity sensors showed a linearity in the humidity range of 0 %RH to 80 %RH. These results reveal that MIS and MIM $CN_{X}$ capacitive humidity sensors can be used for Si based micro-humidity sensors.

• Applied Science and Convergence Technology
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• v.24 no.3
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• pp.53-59
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• 2015

The field-effect transistors (FETs) with a graphene-based p-n junction channel were fabricated using the patterned self-assembled monolayers (SAMs). The self-assembled 3-aminopropyltriethoxysilane (APTES) monolayer deposited on $SiO_2$/Si substrate was patterned by hydrogen plasma using selective coating poly-methylmethacrylate (PMMA) as mask. The APTES-SAMS on the $SiO_2$ surface were patterned using selective coating of PMMA. The APTES-SAMs of the region uncovered with PMMA was removed by hydrogen plasma. The graphene synthesized by thermal chemical vapor deposition was transferred onto the patterned APTES-SAM/$SiO_2$ substrate. Both p-type and n-type graphene on the patterned SAM/$SiO_2$ substrate were fabricated. The graphene-based p-n junction was studied using Raman spectroscopy and X-ray photoelectron spectroscopy. To implement low voltage operation device, via ionic liquid ($BmimPF_6$) gate dielectric material, graphene-based p-n junction field effect transistors was fabricated, showing two significant separated Dirac points as a signature for formation of a p-n junction in the graphene channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.59-59
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• 2009

The efficiency of CMOS technology has been developed in uniform rate. However, there was a limitation of reducing the thickness of Gate-oxide since the thickness of Gate Dielectric is also reduced so an amount of leakage current is grow. In order to solve this problem, the semiconductor device which has a dual gate is used widely. This paper presents a method and a necessity for making the Gate Stack of TFT. Before Using test devices to measure values, stacking $SiN_x$ on a wafer test was conducted.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.6
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• pp.410-415
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• 1999

$Ba_{1-x}Sr_xTiO_3$ thin films with various ratio of Sr (X = 0.4, 0.5, 0.6) were grown $Pt/TiN/SiO_2/Si$ subastrate by RF magnetron sputtering deposition. As, Ag, and Cu films were deposited on $Ba_{1-x}Sr_xTiO_3$ thin films as top electrodes by using a thermal evaporator. The electrical properties of $Ba_{1-x}Sr_xTiO_3$ thin films for various compositions were characterized and the physical properties at interface between $Ba_{1-x}Sr_xTiO_3$ thin films and top electrodes were evaluated in terms of the work function difference. At x =0.5, the degradation of capacitance is lower to the other compositions. As negative biasapplied, the specimen with Cu top electrode has board saturation region and low leakage current since work function of Cu is bigger than other electrodes.$ Ba_{0.5}Sr_{0.5}TiO_3$ thin films with Cu top electrode, the dielectric constant was measured to the value of 354 at 1 kHz and the leakage current was obtained to the value of $5.26\times10^{-6}A/cm2$ at the forward bias of 2 V.

• Korean Journal of Materials Research
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• v.11 no.5
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• pp.367-371
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• 2001

In this paper, theS $r_2$(T $a_{1-x}$ , N $b_{x}$)$_2$ $O_{7}$(STNO) films among ferroelectric materials having a low dielectric constant for metal-ferroelectric-semiconductor field effect transistor(MFS-FET) were discussed. The STNO thin films were deposited on p-type Si(100) at room temperature by co-sputtering with S $r_2$N $b_2$ $O_{7(SNO)}$ ceramic target and T $a_2$ $O_{5}$ ceramic target. The composition of STNO thin films was varied by adjusting the power ratios of SNO target and T $a_2$ $O_{5}$ target. The STNO films were annealed at 8$50^{\circ}C$, 90$0^{\circ}C$ and 9$50^{\circ}C$ temperature in oxygen ambient for 1 hour. The value of x has significantly influenced the structure and electrical properties of the STNO films. In the case of x= 0.4, the crystallinity of the STNO films annealed at 9$50^{\circ}C$ was observed well and the memory windows of the Pt/STNO/Si structure were 0.5-8.3 V at applied voltage of 3-9 V and leakage current density was 7.9$\times$10$_{08}$A/$\textrm{cm}^2$ at applied voltage of -5V.of -5V.V.V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.93-96
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• 2002

In this study, PZT thin films were fabricated using sol-gel processing onto Si/$SiO_2$/Ti/Pt substrates. PZT sol with different Zr/Ti ratio(20/80, 30/70, 40/60, 52/48) were prepared, respectively. The films were fabricated by using the spin-coating method on substrates. The films were heat treated at $450^{\circ}C$, $650^{\circ}C$ by rapid thermal annealing(RTA). The preferred orientation of the PZT thin films were observed by X-ray diffraction(XRD), and Scanning electron microscopy(SEM). All of the resulting PZT thin films were crystallized with perovskite phase. The fine crystallinity of the films were fabricated. Also, we found that the ferroelectric properties from the dielectric constant of the PZT thin films were over 600 degrees, P-E hysteresis constant. And the leakage current densities of films were lower than $10^{-8}A/cm^2$. It is concluded that the PZT thin films by sol-gel process to be convinced of application for ferroelectric memory device.

• Korean Journal of Materials Research
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• v.20 no.11
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• pp.606-610
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• 2010

Films consisting of a silicon quantum dot superlattice were fabricated by alternating deposition of silicon rich silicon nitride and $Si_3N_4$ layers using an rf magnetron co-sputtering system. In order to use the silicon quantum dot super lattice structure for third generation multi junction solar cell applications, it is important to control the dot size. Moreover, silicon quantum dots have to be in a regularly spaced array in the dielectric matrix material for in order to allow for effective carrier transport. In this study, therefore, we fabricated silicon quantum dot superlattice films under various conditions and investigated crystallization behavior of the silicon quantum dot super lattice structure. Fourier transform infrared spectroscopy (FTIR) spectra showed an increased intensity of the $840\;cm^{-1}$ peak with increasing annealing temperature due to the increase in the number of Si-N bonds. A more conspicuous characteristic of this process is the increased intensity of the $1100\;cm^{-1}$ peak. This peak was attributed to annealing induced reordering in the films that led to increased Si-$N_4$ bonding. X-ray photoelectron spectroscopy (XPS) analysis showed that peak position was shifted to higher bonding energy as silicon 2p bonding energy changed. This transition is related to the formation of silicon quantum dots. Transmission electron microscopy (TEM) and electron spin resonance (ESR) analysis also confirmed the formation of silicon quantum dots. This study revealed that post annealing at $1100^{\circ}C$ for at least one hour is necessary to precipitate the silicon quantum dots in the $SiN_x$ matrix.