• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.335-340
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• 2013

In this study, the plasma etching of the TaN thin film with $CH_4/BCl_3/Ar$ gas chemistries was investigated. The etch rate of the TaN thin film and the etch selectivity of TaN to $SiO_2$ was studied as a function of the process parameters, including the amount of $CH_4$. X-ray photoelectron spectroscopy (XPS) and Field-emission scanning electron microscopy (FE-SEM) was used to investigate the chemical states of the surface of the TaN thin film.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.74-74
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• 2009

Titanium nitride has been used as hardmask for semiconductor process, capacitor of MIM type and diffusion barrier of DRAM, due to it's low resistivity, thermodynamic stability and diffusion coefficient. Characteristics of the TiN film are high intensity and chemical stability. The TiN film also has compatibility with high-k material. This study is an experimental test for better condition of TiN film etching process. The etch rate of TiN film was investigated about etching in $BCl_3/Ar/O_2$ plasma using the inductively coupled plasma (ICP) etching system. The base condition were 4 sccm $BCl_3$ /16 sccm Ar mixed gas and 500 W the RF power, -50 V the DC bias voltage, 10 mTorr the chamber pressure and $40\;^{\circ}C$ the substrate temperature. We added $O_2$ gas to give affect etch rate because $O_2$ reacts with photoresist easily. We had changed $O_2$ gas flow rate from 2 sccm to 8 sccm, the RF power from 500 W to 800 W, the DC bias voltage from -50 V to -200 V, the chamber pressure from 5 mTorr to 20 mTorr and the substrate temperature from $20\;^{\circ}C$ to $80\;^{\circ}C$.

• Transactions on Electrical and Electronic Materials
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• v.13 no.6
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• pp.287-291
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• 2012

We investigated the etching characteristics of TaN thin films in an $O_2/BCl_3/Cl_2/Ar$ gas using a high density plasma (HDP) system. A maximum etch rate of the TaN thin films and the selectivity of TaN to $SiO_2$ were obtained as 172.7 nm/min and 6.27 in the $O_2/BCl_3/Cl_2/Ar$ (3:2:18:10 sccm) gas mixture, respectively. At the same time, the etch rate was measured as a function of the etching parameters, such as the RF power, DC-bias voltage, and process pressure. The chemical states on the surface of the etched TaN thin films were investigated using X-ray photoelectron spectroscopy. Auger electron spectroscopy was used for elemental analysis on the surface of the etched TaN thin films. These surface analyses confirm that the surface of the etched TaN thin film is formed with the nonvolatile by-product.

• Applied Chemistry for Engineering
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• v.16 no.6
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• pp.853-856
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• 2005

Inductively coupled plasma reactive ion etching of magnetic tunnel junction (MTJ) stack, which is one of the key elements in magnetic random access memory, was studied. The MTJ stacks were patterned in nanometer size by electron(e)-beam lithography, and TiN thin films were employed as a hard mask. The etch process of TiN hard mask was examined using Ar, $Cl_2/Ar$, and $SF_6/Ar$. The TiN hard mask patterned by e-beam lithography was first etched and then the etching of MTJ stack was performed. The MTJ stacks were etched using Ar, $Cl_2/Ar$, and $BCl_3/Ar$ gases by varying gas concentration and pressure.

• Proceedings of the Korean Vacuum Society Conference
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• 2004.08a
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• pp.226-226
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• 2004

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.104-104
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• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.406-406
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• 2010

일반적으로, 나노스케일의 MOS 소자에서는 게이트 절연체 두께가 감소함에 따라 tunneling effect의 증가로 인해 PID (plasma induced damage)로 인한 소자 특성 저하 현상을 감소하는 추세로 알려져 있다. 하지만 요즘 많이 사용되고 있는 high-k 게이트 절연체의 경우에는 오히려 더 많은 charge들이 trapping 되면서 PID가 오히려 더 심각해지는 현상이 나타나고 있다. 이러한 high-k 게이트 식각 시 현재는 주로 Hf-based wet etch나 dry etch가 사용되고 있지만 gate edge 영역에서 high-k 게이트 절연체의 undercut 현상이나 PID에 의한 소자특성 저하가 보고되고 있다. 본 연구에서는 이에 차세대 MOS 소자의 gate stack 구조중 issue화 되고 있는 metal gate 층과 gate dielectric 층의 식각공정에 각각 중성빔 식각과 중성빔 원자층 식각을 적용하여 전기적 손상 없이 원자레벨의 정확한 식각 조절을 해줄 수 있는 새로운 two step 식각 공정에 대한 연구를 진행하였다. 먼저 TiN metal gate 층의 식각을 위해 HBr과 $Cl_2$ 혼합가스를 사용한 중성빔 식각기술을 적용하여 100 eV 이하의 에너지 조건에서 하부층인 $HfO_2$와 거의 무한대의 식각 선택비를 얻었다. 하지만 100 eV 조건에서는 낮은 에너지에 의한 빔 스케터링으로 실제 패턴 식각시 etch foot이 발생되는 현상이 관찰되었으며, 이를 해결하기 위하여 먼저 높은 에너지로 식각을 진행하고 $HfO_2$와의 계면 근처에서 100 eV로 식각을 해주는 two step 방법을 사용하였다. 그 결과 anistropic 하고 하부층에 etch stop된 식각 형상을 관찰할 수 있었다. 다음으로 3.5nm의 매우 얇은 $HfO_2$ gate dielectric 층의 정확한 식각 깊이 조절을 위해 $BCl_3$와 Ar 가스를 이용한 중성빔 원자층 식각기술을 적용하여 $1.2\;{\AA}$/cycle의 단일막 식각 조건을 확립하고 약 30 cycle 공정시 3.5nm 두께의 $HfO_2$ 층이 완벽히 제거됨을 관찰할 수 있었다. 뿐만 아니라, vertical 한 식각 형상 및 향상된 표면 roughness를 transmission electron microscope(TEM)과 atomic force microscope (AFM)으로 관찰할 수 있었다. 이러한 중성빔 식각과 중성빔 원자층 식각기술이 결합된 새로운 gate recess 공정을 실제 MOSFET 소자에 적용하여 기존 식각 방법으로 제작된 소자 결과를 비교해 본 결과 gate leakage current가 약 one order 정도 개선되었음을 확인할 수 있었다.