• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.18-24
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• 2011

In multibit Sigma-Delta Modulator, one of the DEM(Dynamic Element Matching) techniques which is DWA(Data Weighted Averaging) is widely used to get rid of non-linearity caused by mismatching of capacitor that is unit element of feedback DAC. In this paper, by adjusting clock timing used in existing DWA architecture, 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. After designing the 3rd 3-bit SC(Switched Capacitor) Sigma-Delta Modulator by using the proposed DWA architecture, 0.1% of mismatching into unit element in input frequency 20 kHz and sampling frequency 2.56 MHz. As a consequence of the simulation, It was able to get the same resolution as the existing architecture and was able to reduce the number of MOS Tr. by 222.

• ETRI Journal
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• v.31 no.4
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• pp.393-398
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• 2009

The operation of a first-order 2-bit adaptive sigma-delta modulation system is described and discussed in this paper. The system operation is based on the combination of both "memory" and "look-ahead" estimation in the employed step-size adaptation algorithm of the basic quantizer. In comparison to simple systems and other adaptive sigma-delta systems, computer simulation results show that these features of the described system are responsible for the high SNR values and the extended dynamic range achieved for AC signals as well as the noise power reduction of almost 10 dB and the complete elimination of the idle tones for DC signals. However, such an advantageous performance requires the least possible multiplicative error accumulation, and this cannot be achieved without analog circuits of the highest possible accuracy.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.5
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• pp.122-131
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• 1999

저주파의 아날로그 신호를 디지털 신호로 변환하기 위해 sigma-delta 아날로그-디지털 변환기의 이용이 용이하다. 이 변환기는 변조기와 디지털 필터로 구성되는데 본 논문에서는 변조기에 대해서만 언급한다. 모델링을 통해 14비트 분해능을 갖는 2차 sigma-delta 변조기를 설계하기 위한 변조기의 구성요소 즉 연산 증폭기, 적분기, 내부 ADC 및 DAC의 최대 허용 에러 범위를 규정하였으며, 이를 토대로 연산증폭기, 2비트 ADC 및 DAC 등을 설계·검증하고, 이들을 서로 연결하여 2차 sigma-delta 변조기를 구성하였다. 3비트 ADC의 기준전압을 조절하여 변조기 성능 향상을 도모하였으며, 내부 DAC를 축전기 및 간단한 제어회로로 구성하여 비선형성 에러를 최소화하였다. 설계된 각각의 구성요소들은 모델링에서 정의된 에러 범위를 모두 만족하였으며, 전체 변조기는87㏈의 입력범위와 87㏈의 최대 신호 대 잡음 비를 가졌다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.627-628
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• 2006

A low-voltage switched-capacitor $2^{nd}$-order $\Sigma\Delta$ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the $\Sigma\Delta$ loop. These features greatly relax the DC gain and output swing requirements for Op-Amp in the low-voltage $\Sigma\Delta$ modulator. Implemented by a 0.18-${\mu}m$ CMOS technology, the $\Sigma\Delta$ modulator satisfies performance requirements for WCDMA and CDMA2000 standards.

• ETRI Journal
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• v.30 no.4
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• pp.535-545
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• 2008

This paper introduces a systematic top-down and bottom-up design methodology to assist the designer in the implementation of continuous-time (CT) cascade sigma-delta (${\Sigma}{\Delta}$) modulators. The salient features of this methodology are (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process, (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity, (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance, and (d) use of Pareto-optimal fronts of building blocks to reduce re-design iterations. The applicability of this methodology will be illustrated via the design of a 12-bit 20 MHz CT ${\Sigma}{\Delta}$ modulator in a 1.2 V 130 nm CMOS technology.

• Bulletin of the Korean Mathematical Society
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• v.49 no.6
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• pp.1131-1145
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• 2012

The purpose of this paper is to use an appropriate variational framework to discuss the boundary value problem with p-Laplacian type operators $$\{({\alpha}(t,x^{\Delta}(t)))^{\Delta}-a(t){\phi}_p(x^{\sigma}(t))+f({\sigma}(t),x^{\sigma}(t))=0,\;{\Delta}-a.e.\;t{\in}I\\x^{\sigma}(0)=0,\\{\beta}_1x^{\sigma}(1)+{\beta}_2x^{\Delta}({\sigma}(1))=0,$$ where ${\beta}_1$, ${\beta}_2$ > 0, $I=[0,1]^{k^2}$, ${\alpha}({\cdot},x({\cdot}))$ is an operator of $p$-Laplacian type, $\mathbb{T}$ is a time scale. Some sufficient conditions for the existence of constant-sign solutions are obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.50-59
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• 2007

[ $0.18-{\mu}m$ ] CMOS 1.2-V 2nd-order ${\Sigma}{\Delta}$ modulator with full-feedforward topology is designed. Using full-feedforward topology makes op-amp performance requirements much less stringent, therefore it has been adopted as a good candidate for low-voltage low-power applications throughout the world. Also, ${\Sigma}{\Delta}$ modulator is designed with top-down design approach, therefore various nonideal effects of op-amp are modeled in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.107-114
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• 2004

This paper presents block and timing diagrams of the DWA(Data Weighted Averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the MATLAB modeling, the optimized coefficients of the integrators are obtained to design the modulator. The fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed third-order multibit modulator is fabricated in a 0.35${\mu}{\textrm}{m}$ CMOS process. The modulator achieves 75dB signal-to-noise ratio and 74dB dynamic range at 1.2Vp-p 825kHz input signal and 52.8MHE sampling frequency.

• ETRI Journal
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• v.30 no.3
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• pp.377-382
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• 2008

A novel power amplifier for a polar transmitter is proposed to achieve better spectral performance for a wideband envelope signal. In the proposed scheme, 2-bit sigma-delta (${\Sigma}{\Delta}$) modulation of the envelope signal is introduced, and the power amplifier configuration is modified in a binary form to accommodate the 2-bit digitized envelope signals. The 2-bit ${\Sigma}{\Delta}$ modulator lowers the noise of the envelope signal by fine quantization and thus enhances the spectral property of the RF signal. The Ptolemy simulation results of the proposed structure show that the spectral noise is reduced by 10 dB in a full transmit band of the EDGE system. The dynamic range is also enhanced. Since the performance is improved without increasing the over-sampling ratio, this technique is best suited for wireless communication with high data rates.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.9
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• pp.31-38
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• 2009

In this paper, we propose new gain optimization method for Sigma-Delta A/D converters. First, in proposed method, the 10 candidates are selected through SNR maximization for Sigma-Delta modulator. After then, it is shown that optimum gains can be obtained through MSE calculation for CIC decimation filter. In the simulation, The proposed method has advantages which utilize SNR maximization for modulator and MSE minimization for CIC decimation later. The more candidates are chosen in SNR maximization for modulator, the better gains can be obtained in MSE minimization for CIC decimation filter.