Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

Characterization of gate oxide breakdown in junctionless amorphous InGaZnO thin film transistors

무접합 비정질 InGaZnO 박막 트랜지스터의 게이트 산화층 항복 특성

  • Chang, Yoo Jin (Department of Electronic Engineering, Incheon National University) ;
  • Seo, Jin Hyung (Department of Electronic Engineering, Incheon National University) ;
  • Park, Jong Tae (Department of Electronic Engineering, Incheon National University)
  • Received : 2017.08.16
  • Accepted : 2017.09.05
  • Published : 2018.01.31
Download PDF
⟨ Previous Next ⟩

Abstract

Junctionless amorphous InGaZnO thin film transistors with different film thickness have been fabricated. Their device performance parameters were extracted and gate oxide breakdown voltages were analyzed with different film thickness. The device performances were enhanced with increase of film thickness but the gate oxide breakdown voltages were decreased. The device performances were enhanced with increase of temperatures but the gate oxide breakdown voltages were decreased due to the increased drain current. The drain current under illumination was increased due to photo-excited electron-hole pair generation but the gate oxide breakdown voltages were decreased. The reason for decreased breakdown voltage with increase of film thickness, operation temperature and light intensity was due to the increased number of channel electrons and more injection into the gate oxide layer. One should decide the gate oxide thickness with considering the film thickness and operating temperature when one decides to replace the junctionless amorphous InGaZnO thin film transistors as BEOL transistors.

박막 두께가 다른 무접합 비정질 InGaZnO 막막 트랜지스터를 제작하고 박막 두께, 동작 온도 및 빛의 세기에 따른 소자의 성능 변수를 추출하고 게이트 산화층 항복전압을 분석하였다. 박막의 두께가 클수록 소자의 성능이 우수하나 드레인 전류의 증가로 게이트 산화층 항복전압은 감소하였다. 고온에서도 소자의 성능은 개선되었으나 게이트 산화층 항복 전압은 감소하였다. 빛의 세기가 증가할수록 광자에 의해 생성된 전자로 드레인 전류는 증가 하였으나 역시 게이트 산화층 항복전압은 감소하였다. 박의 두께가 클수록, 고온일수록, 빛의 세기가 강할수록 채널의 전자수가 증가하여 산화층으로 많이 주입되었기 때문이다. 무접합 a-IGZO 트랜지스터를 BEOL 트랜지스터로 사용하기 위해서는 박막 두께 및 동작 온도를 고려해서 산화층 두께를 설정해야 됨을 알 수 있었다.

Keywords

References

  1. T. Y. Hsieh, T. C. Chang, T. C. Chen, and M. Y. Tsai, "Review of Present Reliability Challenges in Amorphous In-Ga-Zn-O Thin Film Transistors," ECS Journal of Solid State Science and Technology, vol.3, no. 9, pp. Q3058-Q3070, August 2014. https://doi.org/10.1149/2.013409jss
  2. T. Onuki, W. Uesugi, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T.R., Yew, J.Y. Wu, C.C. Shuai, S.H. Wu, J. Myers, K. Doppler, M. Fujita, S. Yamazaki, "Embeded memory and ARM cortex-M0 core using 60nm C-axis aligned crystalline Indium-Gallium_Zinc Oxide FET integrated with 65nm Si CMOS," IEEE Journal of Solid-State Circuits, vol.52, no.4, pp. 925-932, April 2017. https://doi.org/10.1109/JSSC.2016.2632303
  3. K. Hatasako, N. Tetsuya, M. Hane, S. Maegawa, "Past and future technology for Mixed signal LSI," IEICE Transaction Electron, vol.E97-C, no.4, pp. 238-244, April 2014. https://doi.org/10.1587/transele.E97.C.238
  4. L.J.Chi, M.J. Yu, Y.H. Chang, T.H. Hou, "1-V full swing depletion load a-In-Ga-Zn-O inverters for back- end-of-line compatible 3D integration," IEEE Electron Device Letters, vol. 37, no. 4, pp. 441-443, April 2016. https://doi.org/10.1109/LED.2016.2535124
  5. K. Kaneko, H. Sunamura, M. Narihiro, S. Saito, N. Furutake, M. Hane, Y. Hayashi, "Operation of functional circuit elements using BEOL transistor with InGaZnO channel for on-chip high/low voltage bridging I/O and high current switches," Symposium on VLSI Technology Digest of Technical Papers, Honolulu, pp. 123-124, June 2012.
  6. H. Sunamura, K. Kaneko, N. Furutake, N. Ikarashi, M. Hane, Y. Hayashi, "High On/Off ratio P-type oxide based transistors integrated onto Cu interconnects for on-chip high/low voltage bridging BEOL CMOS I/O," IEEE International Electron Devices Meeting, San francisco, pp. 447-450, December 2012.
  7. J.P. Colinge, C.W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. Oneill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistor without junction," Nature Nanotecnology, vol. 5, no. 3, pp. 225-229, March 2010. https://doi.org/10.1038/nnano.2010.15
  8. S.M. Kim, C.G. Yu, W.J, Cho, J.T. Park, "Device characterization and design guideline of amorphous InGaZnO junctionless thin film transistors," IEEE Transactions on Electron Devices, vol. 64, no. 6, pp. 2526-2532, June 2017. https://doi.org/10.1109/TED.2017.2696048
  9. J. Zhou, G. Wu, L. Guo, L. Zhu, and Q. Wan, "Flexible transparent junctionless TFTs with oxygen-tuned Indium-Zinc-Oxide channels," IEEE Electron Device Letters, vol. 34, no. 2, pp. 888-890, February 2013. https://doi.org/10.1109/LED.2013.2260819
  10. C.W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J.P. Colinge, "Performance estimation of junctionless multigate transistors," Solid-State Electronics, vol. 54, pp. 97-103, February 2010. https://doi.org/10.1016/j.sse.2009.12.003
  11. X. Ding, J. Zhang, . Li, H. Zhang, W. Shi, X. Jiang, Z, Zhang, "Influence of the InGaZnO channel layer thickness on the performance of thin film transistors," Superlattice and Microstructures, vol. 63, pp. 70-78, August 2013. https://doi.org/10.1016/j.spmi.2013.08.017
  12. M. Nakata, H. Tsuji, H. sao, Y. Nakajima, Y. Fujisaki, T. Takei, T. Yamamoto, and H. Fujikako, "Influence of oxide semiconductor thickness on thin-film transistor characteristics," Japanese Journal of Applied Physics, vol. 52, pp. 03BB04-1-5, March 2013. https://doi.org/10.7567/JJAP.52.03BB04
  13. C. Chen, K. Abe, H. Kunomi, J. Kanicki, "Density of state of a-InGaZnO from temperature dependent field effect studies," IEEE Transactions on Electron Devices, vol. 56, no. 6, pp. 1177-1181, June 2009. https://doi.org/10.1109/TED.2009.2019157
  14. J. Martins, P. bahubalindrrun, A. Rovisco, A. Kiazadeh, R. Martins, E. Fortunato, P. Barquinha, "Bias stress and temperature impact on InGaZnO TFTs and circuits," Materials, vol. 10, pp. 680-689, June 2017. https://doi.org/10.3390/ma10060680
  15. S. Lee, M. Mativenga, J. Jang, "Removal of negative bias illumination stress instability in amorphous InGaZnO thin film transistors by top gate offset structure," IEEE Electron Device Letters, vol. 35, no. 9, pp. 930-932, June 2014. https://doi.org/10.1109/LED.2014.2333014
  16. M.P. hung, D. Wang, J. Jiang, M. furuta, "Negative bias and illumination stress induced electron trapping at back channel interface of InGaZnO thin film transistors," ECS Solid State Letters, vol. 3, no. 3, pp. Q13-Q16, January 2014. https://doi.org/10.1149/2.010403ssl
  17. M.J. Yu, R.P. Lin, Y.H. Chang, T.H. Hou, "High voltage amorphous InGaZnO TFT with $Al_2O_3$ high-K dielectric for low temperature monolithic 3-D integration," IEEE Transactions on Electron Devices, vol. 63, no. 10, pp. 3944-3949, October 2014. https://doi.org/10.1109/TED.2016.2598396
  18. D. Jay, S.S. Cheng, C.Y. Yang, C.W. Ou, Y.C. Chung, M.C. Wu, C.W. Chu, "Dependence of channel thickness on the performance of $In_2O_3$ thin film transistors," Journal of Physics D: Applied Physics, vol. 41, pp. 09006-09015, March 2008.
  19. J.F. Verweij, J.H. Klootwijk, "Dielectric breakdown I: A review of oxide breakdown," Microelectronics Journal, vol. 27, no. 7, pp. 611-622, July 1996. https://doi.org/10.1016/0026-2692(95)00104-2
  20. C.C. Chen, C.Y. Chang, C.H. Chien, T.Y. Huang, "Temperature accelerated dielectric breakdown in ultrathin gate oxides," Applied Physics Letters, vol. 74, no. 24, pp. 3708-3710, April 1999. https://doi.org/10.1063/1.123228
  21. J.S. Jeon, S.H. Jo, H.J. Choi, J.T. Park, "Effect of thin film thickness on device instability of amorphous InGaZnO junctionless transistors," Journal of the Korean Institute of Informantion and Communication Engineering, vol. 21, no. 9, pp. 1627-1634, September 2017.