ETRI Journal

  • 제34권1호
  • /
  • Pages.44-54
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  • 2012
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  • 1225-6463(pISSN)
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  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
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On-Chip Debug Architecture for Multicore Processor

  • Park, Hyeong-Bae (Department of Electronics and Electrical Engineering, Pusan National University) ;
  • Xu, Jing-Zhe (Department of Electronics and Electrical Engineering, Pusan National University) ;
  • Kim, Kil-Hyun (Department of Electronics and Electrical Engineering, Pusan National University) ;
  • Park, Ju-Sung (Department of Electronics and Electrical Engineering, Pusan National University)
  • 투고 : 2011.03.21
  • 심사 : 2011.07.18
  • 발행 : 2012.02.01
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초록

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

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참고문헌

  1. W. Wolf, A. Jerraya, and G. Martin, "Multiprocessor System-on- Chip (MPSoC) Technology," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 10, Oct. 2008, pp. 1701- 1713.
  2. T. Dorta et al., "Overview of FPGA-Based Multiprocessor Systems," Int. Conf. Reconfigurable Comput. FPGAs, 2009, pp. 273-278.
  3. G. Martin, "Overview of the MPSoC Design Challenge," 43rd ACM/IEEE Design Autom. Conf., 2006, pp. 274-279.
  4. A.B.T. Hopkins and K. McDonald-Maier, "Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores," IEEE Trans. Comput., vol. 55, no. 2, Feb. 2006, pp. 174-184, doi:10.1109/TC.2006.22.
  5. ARM Ltd. Embedded-ICE Block Specification. Available: http://www.arm.com
  6. MIPS Technologies Inc. EJTAG Trace Control Block Specification. Available: http://www.mips.com
  7. JTAGPPC Controller. Available: http://www.xilinx.com
  8. L. Lian et al., "Design and Implementation of A Debugging System for OpenRISC Processor," 2nd ASID Conf., 2008, pp. 368-371.
  9. ARM Ltd. Embedded Trace Macrocell (ETM) Block Specification. Available: http://www.arm.com
  10. PDtraceTM Interface Specification, MD00136, May 14, 2003. http://www.mips.com
  11. B. Vermeulen, "Functional Debug Techniques for Embedded Systems," IEEE Design Test Comput., vol. 25, no. 3, 2008, pp. 208-215.
  12. H.F. Ko, A.B. Kinsman, and N. Nicolici, "Design-for-Debug Architecture for Distributed Embedded Logic Analysis," Very Large Scale Integr. Syst., vol. 13, 2010, pp. 1-14.
  13. K. Goossens et al., "Transaction-Based Communication-Centric Debug," Proc. Int. Symp. Netw. On-Chip, May 2007.
  14. B. Vermeulen, K. Goossens, and S. Umrani, "Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip," Proc. Int. Symp. Netw. On- Chip, 2008, pp. 3-12.
  15. B. Vermeulen and K. Goossens, "A Network-on-Chip Monitoring Infrastructure for Communication-Centric Debug of Embedded Multiprocessor SoCs," Int. Symp. VLSI Design, Automation Test, 28-30 Apr. 2009, pp. 183-186.
  16. N. Stollon et al., "Multi-core Embedded Debug for Structured ASIC Systems," Proc. DesignCon, 2004.
  17. R. Leatherman and N. Stollon, "An Embedded Debugging Architecture for SoCs," IEEE Potentials, vol. 24, no. 1, 2005, pp. 12-16.
  18. ARM11MPCore Specification. Available: http://www.arm.com
  19. W. Orme, "Debug and Trace for Multicore SoCs," Sept. 2008. Available: http://www.arm.com
  20. B. Vermeulen et al., "Overview of Debug Standardization Activities," IEEE Design Test Comput., vol. 25, no. 3, May 2008, pp. 258-267.
  21. H. Yi, S. Park, and S. Kundu, "On-Chip Support for NoC-based SoC Debugging," IEEE Trans. Circuits and Syst. Part I: Regular Papers, vol. 57, no. 7, 2010, pp. 1608-1617.
  22. S. Tang and Q. Xu, "A Multi-core Debug Platform for NoCBased Systems," Proc. Design, Autom. Test Europe Conf. Exhibition, Apr. 2007, pp. 1-6.
  23. S. Tang and Q. Xu, "A Debug Probe for Concurrently Debugging Multiple Embedded Cores and Inter-core Transactions in NoCBased Systems," Conf. Asia South Pacific Design Autom., Seoul, Rep. of Korea, 2008, pp. 416-421.
  24. L. Fiorin, G. Palermo, and C. Silvano., "MPSoCs Run-Time Monitoring through Networks-on-Chip," Proc. Conf. Design, Automation Test Europe Conf. Exhibition, 2009, pp. 558-561.
  25. CoreSight On-Chip Trace and Debug Specification. Available: http://www. arm.com
  26. B. Vermeulen and S. Bakker, ''Debug Architecture for the En-II System Chip,'' Comput. Digit. Techn., IET, vol. 1, no. 6, Nov. 2007, pp. 678-684.
  27. IEEE Std. 1149.1a-1993, "Test Access Port and Boundary-Scan Architecture," IEEE, 1993.
  28. H. Park et al., "Design of On-Chip Debugging System Using GNU Debugger," IEEK, vol. 46, no. 1, 2009, pp. 24-38.
  29. I.-J. Huang et al., "A Retargetable Embedded In-circuit Emulation Module for Microprocessors," IEEE Design Test Comput., vol. 19, no. 4, July-Aug. 2002, pp. 28-38.
  30. D.A. Patterson and J.L. Hennessy, Comput. Organization Design, 4th ed., Morgan Kaufmann Publishers, 2009, p. 336.
  31. H. Hao and R. Avra, "Structured Design-for-Debug-the SuperSPARCTMII Methodology and Implementation," Proc. Int. Test Conf., 1995, pp. 175-183.
  32. H. Hao and K. Bhabuthmal, "Clock Controller Design in SuperSPARCTMII Microprocessor," Proc. Int. Test Conf. Comput. Design, 1995, pp. 124-129.
  33. G.J. van Rootselaar and B. Vermeulen, "Silicon Debug: Scan Chains Alone Are Not Enough," Int. Test Conf., 1999, p. 892.
  34. G.R. Alves and J.M.M. Ferreira, "From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1," Proc. 17th IEEE VLSI Test Symp., Los Alamitos, CA: IEEE CS Press, 1999, pp. 473-480.
  35. A. Hopkins and K. McDonald-Maier, ''Debug Support for Complex Systems On-Chip: A Review,'' IEE Proc. Comput. Digit. Tech., vol. 153, no. 4, July 2006, pp. 197-207.
  36. B. Vermeulen, T. Waayers, and S. Bakker, "IEEE 1149.1- Compliant Access Architecture for Multiple Core Debug on Digital System Chips," Proc. Int. Test Conf., Oct. 2002, pp. 55-63
  37. R. Stallman, R. Pesch, and S. Shebs, Debugging with GDB: The GNU Source-Level Debugger, Free Software Foundation.
  38. Open On-Chip Debugger. Available: http://openocd.berlios.de/ web/

피인용 문헌

  1. Easily Adaptable On-Chip Debug Architecture for Multicore Processors vol.35, pp.2, 2012, https://doi.org/10.4218/etrij.13.0112.0487