• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.226-232
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• 2005

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some 14% performance enhancement and 50% gate count reduction compared to the conventional ones.

• Proceedings of the IEEK Conference
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• summer
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• pp.61-65
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• 2004

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage reducing overall debugging time. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some $14\%$ performance enhancement and $50\%$ gate count reduction compared to the conventional ones.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.2
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• pp.31-42
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• 2014

Debugger systems are necessary to apply dynamic program analysis when evaluating security properties of embedded system software. It may be possible to make the use of software-based debugger and/or DBI framework if target devices support general purpose operating systems, however, constraints on applicability as well as environmental transparency might be incurred thereby hindering overall analyzability. Analysis with JTAG (IEEE 1149.1) debugging devices can overcome these difficulties in that no change would be involved in terms of internal software environment. In that sense, JTAG API can facilitate to practically perform dynamic program analysis for evaluating security properties of target device software. In this paper, we introduce an implementation of JTAG API to enable analysis of ARM core based embedded systems. The API function set includes the categories of debugger and target device controls: debugging environment and operation. To verify API applicability, we also provide example analysis tool implementations: our JTAG API could be used to build kernel function fuzzing and live memory forensics modules.

• ETRI Journal
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• v.35 no.2
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• pp.301-310
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• 2013

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.329-332
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• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.943-945
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• 2004

임베디드 소프트웨어는 타겟 시스템의 자원과 타이밍에 민감하므로 실제 타겟 시스템과 동일한 환경에서 디버깅해야한다. 이를 위한 기존의 기법들은 타겟 시스템의 자원에 직접적으로 접근하여 시스템 상태를 조사하거나 제어한다. 그러나 이러한 기법들은 내부 신호나 자원에 대한 접근이 제한되어 있는 SoC (System-On-a-Chip) 프로그램을 디버깅하기는 부적합하다. 본 논문에서는 산업 표준화된 JTAG을 기반으로 공개 소프트웨어인 gob를 연동하여 SoC 소프트웨어를 디버깅하는 도구를 제안한다. 따라서 본 도구는 타겟 시스템에 영향을 주지 않고 경제적으로 디버깅할 수 있는 환경을 제공한다.

• ETRI Journal
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• v.34 no.1
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• The KIPS Transactions:PartA
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• v.12A no.7 s.97
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• pp.583-588
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• 2005

To develop SoC program for embedded systems, a tool that can remotely debug from host system is needed. Because the existing remote debugging systems using GDB don't offer information of the SoC program execution in real-time, it is difficult to observe condition of the program execution, and also they have limited characteristics to tools and use costly adaptors. In this paper, a real-time tracking tool that can record SoC status on the nv each execution of the assigned instructions is introduced and an economical USB-JTAG adaptor is proposed. And it is shown that this tool can track the execution of a composed program in the target system based on PXA255 processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.24-38
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• 2009

In this paper, we implement processor debugger based on OCD(On-Chip Debugger). Implemented debugger consist of software debugger that supports a functionality of symbolic debugging, OCD integrated into target processor as a function of debugging, and Interface & Control block which interfaces software debugger and OCD at high speed rates. The debugger supports c/assembly level debugging using software debugger as OCD is integrated into target processor. After OCD block is interfaced with 32bit RISC processor core and then implemented with FPGA, the verification of On-Chip Debugging System is carried out through connecting OCD and Interface & Control block, and SW debugger.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.258-260
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• 2004

The Controller Area Network (CAN) is being widely used in real-time control applications such as automobiles, aircraft, and automated factories. Unfortunately, CAN, in its current form, is not able to either share out the system bandwidth among the different devices fairly or to grant an upper bound on the transmission times experienced by the nodes connected to the communication medium as it happens, for instance, in the token-based networks. In this paper, we present An Application Layer Design for Humanoid Robot in the CAN. Besides introducing the new algorithm, this paper also presents some performance figures obtained using a specially developed software simulator and experimentation for composition of CAN which uses JTAG mode of a parallel debugging., while the behavior of the new algorithm is compared with the traditional CAN systems. in order to see how effective they are.