한국멀티미디어학회논문지 (Journal of Korea Multimedia Society)

  • 제14권5호
  • /
  • Pages.614-621
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  • 2011
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  • 1229-7771(pISSN)
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  • 2384-0102(eISSN)
한국멀티미디어학회 (Korea Multimedia Society)
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Mobile-DTV 응용을 위한 광대역 DCO 설계

Design of a Wide Tuning Range DCO for Mobile-DTV Applications

  • 송성근 (전남대학교 전자컴퓨터공학과) ;
  • 박성모 (전남대학교 전자컴퓨터공학과)
  • 투고 : 2011.01.20
  • 심사 : 2011.04.04
  • 발행 : 2011.05.31
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초록

본 논문은 Mobile-DTV 응용을 위한 광대역 DCO(Digitally Controlled Oscillator)의 설계에 대해 다룬다. DCO는 발전 주파수를 생성하는 회로로 ADPLL(All-digital Phase-locked Loop)의 핵심 블록이다. 본 논문에서는 광대역 DCO 설계를 위해 기존의 Fixed delay chain을 변형한 binary delay chain(BDC) 구조를 제안하였다. 제안된 구조는 $2^i$ 형태로 $0{\leq}i{\leq}n-1$ 범위의 서로 다른 지연시간을 갖는 여러개의 지연셀의 조합을 통해 발진 주파수를 생성한다. BDC 형태는 응용에 맞는 지연셀의 조합과 해상도를 선택할 수 있기 때문에 지연셀의 최적화가 가능하다. 제안된 DCO는 1.8V chartered $0.18{\mu}m$ CMOS 공정을 이용하여 Cadence사의 Spectre RF 툴에서 검증되었다. 실험결과 77MHz~2.07GHz의 주파수 대역파 3ps의 해상도를 나타내었다. 위상잡음은 Mobile-DTV 표준의 최대 주파수인 1675MHz에서 -101dBc/Hz@1MHz를 나타내었고 전력소모는 5.87mW를 나타내었다. 이는 ATSC-M/H, DVB-H, ISDB-T, T-DMB 등 Mobile-DTV의 표준을 만족한다.

This paper presents design of a wide tuning range digitally controlled oscillator(DCO) for Mobile-DTV applications. DCO is the key element of the ADPLL block that generates oscillation frequencies. We proposed a binary delay chain(BDC) structure, for wide tuning range DCO, modifying conventional fixed delay chain. The proposed structure generates oscillation frequencies by delay cell combination which has a variable delay time of $2^i$ in the range of $0{\leq}i{\leq}n-1$. The BOC structure can reduce the number of delay cells because it make possible to select delay cell and resolution. We simulated the proposed DCO by Cadence's Spectre RF tool in 1.8V chartered $0.18{\mu}m$ CMOS process. The simulation results showed 77MHz~2.07GHz frequency range and 3ps resolution. The phase noise yields -101dBc/Hz@1MHz at Mobile-DTV maximum frequency 1675MHz and the power consumption is 5.87mW. The proposed DCO satisfies Mobile-DTV standards such as ATSC-M/H, DVB-H, ISDB-T, T-DMB.

키워드

참고문헌

  1. Liangge Xu, Kari Stadius, Tapio Rapinoja, and Jussi Ryynanen, "Agile Frequency Synthesizer for Cognitive Radios," IEEE Circuit Theory and Design Conf, pp.275-278, 2009.
  2. Sang-Myeong Shin, Dong-Gi Im, and Min-Soo Jung, "Efficient Native Processing Modules for Interactive DTV Middleware Based on the Small Footprint Set-Top Box," Journal of Korea Multimedia Society, Vol.9, No.12, pp.1617-1627, 2006.
  3. Bon-Kee Kim, Tae-Wook Kim, Young-Ho Cho, Min-Su Jeong, Se-Yeob Kim, Hee- Young Yoo, Seong-Mo Moon, Tae-Ju Lee, Jin-Kyu Lim, and Bo-Eun Kim, "A 100㎽ Dual-Band CMOS Mobile-TV Tuner IC for -T-DMB/ DAB and ISDB-T," IEEE Solid- State Circuits Conf, pp.2534-2543. 2006.
  4. Jen-Shiun Chiang and Kuang-Yuan Chen, "The Design of an All-Digital Phase-Locked Loop with Small DCO Hardware and Fast Phase Lock," IEEE Transactions on Circuits and Systems II-analog and digital signal processing, Vol.46, No.7, pp.945-950, 1999. https://doi.org/10.1109/82.775392
  5. P.-L. Chen, C.-C. Chung, J.-N. Yang, and C.-Y. Lee, "A Clock Generator with Cascaded Dynamic Frequency Counting Loops for Wide Multiplication Range Applications," IEEE J. Solid-State Circuits, Vol.41, No.6, pp.1275- 1285, 2006. https://doi.org/10.1109/JSSC.2006.874273
  6. Chen Juan, Fang Shou-hai, and Chen Xin, "A Novel DCPLL with Small-Area and Low- Power DCO for SoC Applications," IEEE Solid-State and Integrated-Circuit Technology Conf, pp.1867-1870, 2008.
  7. T. Olsson and P. Nilsson, "A Digitally Controlled PLL for SoC Application," IEEE J. Solid-State Circuits, Vol.39, No.5, pp.751- 760, 2004. https://doi.org/10.1109/JSSC.2004.826333
  8. Staszewski. R. B, Dirk Leipold, Khurram Muhammad, and Poras T. Balsara, "Digitally Controlled Oscillator(DCO)-Based Architecture for RF Frequency Synthesis in a Deep- Submicrometer CMOS Process," IEEE Transactions on Circuits and Systems II-analog and digital signal processing, Vol.50, No.11, pp.815-823, 2003. https://doi.org/10.1109/TCSII.2003.819128
  9. J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, "A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI," IEEE J. Solid- State Circuits, Vol.43, No.1, pp.42-51, 2008. https://doi.org/10.1109/JSSC.2007.910966
  10. R.-J. Yang and S.-I. Liu, "A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 $\mu$m CMOS Technology," IEEE J. Solid-State Circuits, Vol.42, No.1, pp.2338-2347, 2007. https://doi.org/10.1109/JSSC.2007.906183
  11. Kwang-Hee Choi, Jung-Bum Shin, Jae-Yoon Sim, and Hong-June Park, "An Interpolating Digitally Controlled Oscillator for a Wide- Range All-Digital PLL," IEEE transactions on circuits and system, Vol.56, No.9, pp.2055-2063, 2009. https://doi.org/10.1109/TCSI.2008.2011577
  12. Tomar A., Pokharel R.K., Nizhnik O., and Kanaya H., Yoshida K., "Design of 1.1 ㎓ Highly Linear Digitally-Conrolled Ring Oscillator with Wide Tuning Range," RFIT2007-IEEE International Workshop on Radio-Frequency Integration Technology, pp. 82-85, 2007.
  13. G. Jovanovic, M. Stojcev, "Voltage Controlled Delay Line for Digital Signal," Facta Universitatis, Series: Electronics and Energetic, Vol. 16. No.2, pp.215-232, 2003. https://doi.org/10.2298/FUEE0302215J

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