• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.3
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• pp.44-49
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• 2007

This paper proposes converter that new soft switching active snubber circuit is added, the resonance energy return to life rate doing maximum whole efficiency increase. Proposed converter adds auxiliary switch and resonance inductor, resonance capacitor, two diodes to existing converter, all switch elements play turn-on/turn-off under soft switching condition and minimized switching losses. Conduction loss department is that watch layer bringing back to life resonance energy by input perfectly. These result proved through simulation and an experiment.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.535-538
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• 1994

In this paper, an isolated ZVS-PWM boost converter is proposed for single stage line conversion. For power factor correction, we used the half bridge topology at the primary side of isolation transformer permitting switching devices to operate under ZVS by using circuit parastics and operating at a fixed duty ratio near 50%. Thus the relatively continuous input current distortion and small size input filter are also achievable. The ZVS-PWM boost operation of the proposed converter can be achieved by using the boost inductor $L_f$, main switch $Q_3$, and simple auxiliary circuit at the secondary side of isolation transformer. The secondary side circuit differ from a conventional PWM boost converter by introduction a simple auxiliary circuit. The auxiliary circuit is actived only during a short switching transition time to create the ZVS condition for the main switch as that of the ZVT-PWM boost converter. With a single stage, it is possible to achieve a sinusoidal line current at unity power factor as well as the isolated 48V DC output. Comparing to the two stage schemes, overall effiency of the proposed converter is highly improved due to the effective ZVS of all devices as well as single stage power conversion. Thus, it can be operated at high switching frequency allowing use of small size input filter. Minimum voltage and current stress make it high power application possible.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.3B no.3
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• pp.147-154
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• 2003

This paper presents a high-frequency boost type ZVS-PWM chopper-fed DC-DC power converter with a single active auxiliary edge-resonant snubber at the load stage which can be designed for power conditioners such as solar photovoltaic generation, fuel cell generation, battery and super capacitor energy storages. Its principle operation in steady-state is described in addition to a prototype setup. The experimental results of boost type ZVS-PWM chopper proposed here, are evaluated and verified with a practical design model in terms of its switching voltage and current waveforms, the switching v-i trajectory and the temperature performance of IGBT module, the actual power conversion efficiency, and the EMI of radiated and conducted emissions, and then discussed and compared with the hard switching scheme from an experimental point of view. Finally, this paper proposes a practical method to suppress parasitic oscillation due to the active auxiliary resonant switch at ZCS turn-off mode transition with the aid of an additional lossless clamping diode loop, and can be reduced the EMI conducted emission.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.154-161
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• 2006

This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.2
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• pp.73-80
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• 2003

This Paper Proposes instantaneous following control method to control pulse modulation switching converter by using principle that reset time of integrator is inverse proportion in size of integrator input voltage. proposed control method acts of fixed frequency and control switch calculates time of become turn on and turn off using analog integrator. Duty ratio that express switching time of converter is depended on mean value of switching variable and following time consists in one cycle. Follow to do order exactly stationary state as well as transition state, and controller corrects mean value of control variable and control reference value and control as control error gets into zero. Proposed control method could experimented and know that experiment result and theory are agreeing well through this using the buck converter.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.6
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• pp.460-469
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• 2015

This study's aim is for reducing big data transfer time of IoT healthcare devices by modulating digital bits into Manchester code including zero-voltage idle as information for secondary compressed binary cluster's compartment after two step compression of compressing binary data into primary and secondary binary compressed clusters for each binary clusters having compression benefit of 1 bit or 2 bits. Also this study proposed that as department information of compressed binary clusters, inserting idle signal into Manchester code will have benefit of reducing transfer time in case of compressing binary cluster into secondary compressed binary cluster by 2 bits, because in spite of cost of 1 clock idle, another 1 bit benefit can play a role of reducing 1 clock transfer time. Idle signal is also never consecutive because the signal is for compartment information between two adjacent secondary compressed binary cluster. Voltage transition on basic rule of Manchester code is remaining while inserting idle signal, so DC balance can be guaranteed. This study's simulation result said that even compressed binary data by another compression algorithms could be transferred faster by as much as about 12.6 percents if using this method.