• 아동학회지
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• 제29권5호
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• pp.1-12
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• 2008

This study investigated the development of complex sentences in the early utterances of Korean-Chinese children. The subjects were 47(20 2-year-old, 15 3-year-old, and 12 4-year-old) Korean-Chinese children living in China. Each child's spontaneous natural speech during interaction with his/her caregiver was videotaped for about 30 minutes and analyzed for Korean complex sentences using Kim's(2000) categories and Korean Computerized Language Analysis 2.0(2000). Results showed that older children were higher in Mean Length of Utterance and in number and frequency of word types than younger children. The language development of bilingual children was delayed compared with monolingual children but the developmental sequence between bilingual and monolingual children was similar.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1269-1274
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• 2004

This paper presents a new quantisation algorithm which has the closed-loop form and guarantees the boundness of accumulative error. This algorithm is particularly useful for mobile robot navigation that is usually implemented on embedded systems. If wheel commands of the mobile robot are given by velocity or positional increment at every control instant and quantised due to finite word length of controller's CPU, the quantisation error gets accumulated to causes large position error. Such an error accumulative characteristic is fatal for non wheeled mobile robots or autonomous vehicles with non-holonomic constraint. To solve this problem, we propose a non-error accumulative quantisation algorithm with closed-loop form. We also show it can be extend to a generalized form corresponding to the n-th order accumulation. The boundness of the accumulative quantisation error is investigated by a series of computer simulation. The proposed method is particularly effective to precise navigation control the autonomous mobile robots.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.662-665
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• 2002

This paper describes a novel converter to implement high-speed binary-to-residue conversion for moduli 2$^{n}$ - 1, 2$^{n}$ , 2$^{n}$ +2$^{\alpha}$/($\alpha$$\in$｛0,1,…,n-1｝) without using look-up table. In our implementation, the high-speed converter can be achieved, because of the modulo addition time is independent of the word length of operands by using the Signed-Digit (SD) adders inside the modulo adders. For a LSI implementation of residue SD number system with ordinary binary system, the proposed binary-to-residue converter is the efficient circuit.cient circuit.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.659-662
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• 2005

A parameterized FFT/IFFT core generator (PFFT_CoreGen) is designed, which can be used as an essential IP (Intellectual Property) in various OFDM modem designs. The PFFT_CoreGen generates Verilog-HDL models of FFT cores in the range of 64 ${\sim}$ 2048-point. To optimize the performance of the generated FFT cores, the PFFT_CoreGen can select the word-length of input data, internal data and twiddle factors in the range of 8-b ${\sim}$ 24-b. Some design techniques for low-power design are considered from algorithm level to circuit level.

• 대한음성학회지:말소리
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• 제68권
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• pp.95-114
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• 2008

The recent growing popularity of statistical methods in machine translation requires much more large parallel corpora. A Korean-English parallel corpus, however, is not yet enoughly available, little research on this subject is being conducted. In this paper we present a hybrid method of aligning sentences for Korean-English parallel corpora. We use bilingual news wire web pages, reading comprehension materials for English learners, computer-related technical documents and help files of localized software for building a Korean-English parallel corpus. Our hybrid method combines sentence-length based and word-correspondence based methods. We show the results of experimentation and evaluate them. Alignment results from using a full translation model are very encouraging, especially when we apply alignment results to an SMT system: 0.66% for BLEU score and 9.94% for NIST score improvement compared to the previous method.

• 전자공학회논문지A
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• 제33A권10호
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• pp.168-176
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• 1996

This paper presetns a 2-D DCT architecture adopting accurac y compensator for reducing the hardware complexity and increasing processing speed in VL\ulcornerSI implementation. In the application fields such as moving pictures experts group (MPEG) and joint photographic experts group (JPEG), 2-D DCT processor must be implemented precisely enough to meet the accuracy specifications of the ITU-T H.261. Almost all of 2-D DCT processors have been implemented using many multiplications and accumulations of matrices and vectors. The number of multiplications and accumulations seriously influence on comlexity and speed of 20D DCT processor. In 2-D DCT with fixed-point calculations, the computation bit width must be sufficiently large for the above accuracy specifications. It makes the reduction of hardware complexity hard. This paper proposes the accuracy compensator which compensates the accuracy of the finite word length calculation. 2-D DCT processor with the proposed accuracy compensator shows fairly reduced hardware complexity and improved processing speed.

• Journal of information and communication convergence engineering
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• 제7권4호
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• pp.516-520
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• 2009

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyzed the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the RSA processor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 하계종합학술대회 논문집
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• pp.138-141
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• 1989

In resent years, aided by the power and capability of digital computation, the techniques of Walsh Transform have been exploited for applications in commun- ication and signal processing. This paper presents an approach of FWT by using a 16- bit word-length micro- computer. This FWT implements an in-placed decimation-in-sequency algorithm which improves processing speed and memory storage. Several examples illustrate the process and demonstrate the power spectrum of FWT and that of FFT for the waveforms

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1999년도 제14차 학술회의논문집
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• pp.313-316
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• 1999

In this paper, a quantization algorithm by which the accumulative error can be prevented is presented. In digital control systems, the quantization cannot be avoided because of the finite word length of digital computers. The error due to quantization of the computed values may be tolerable in case of directly using them. In case of using the accumulated values, the error between sum of the original values and that of the quantized values becomes larger as the number of the values to be summed increases. Such an increasing accumulative error is critical for the control of precise NC machines, robots and autonomous vehicles. To solve this problem, a quantization algorithm without the accumulative error is presented. Basically, the algorithm is based on the feedback loop by which the accumulationive of the quantization error can be prevented. The error boundness of the proposed algorithm is proven and a computer simulation is performed to show the validity of the algorithm.