• Title/Summary/Keyword: wireless transceiver

Search Result 212, Processing Time 0.016 seconds

Four Channel Step Up DC-DC Converter for Capacitive SP4T RF MEMS Switch Application (정전 용량형 SP4T RF MEMS 스위치 구동용 4채널 승압 DC-DC 컨버터)

  • Jang, Yeon-Su;Kim, Hyeon-Cheol;Kim, Su-Hwan;Chun, Kuk-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.46 no.2
    • /
    • pp.93-100
    • /
    • 2009
  • This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.

I/Q channel 12-Bit 120MHz CMOS D/A Converter for WLAN (무선랜용 I/Q 채널 12bit 120MHz CMOS D/A 변환기 설계)

  • Ha, Sung-Min;Nam, Tae-Kyu;Seo, Sung-Uk;Shin, Sun-Hwa;Joo, Chan-Yang;Yoon, Kwang-S.
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.11 s.353
    • /
    • pp.83-89
    • /
    • 2006
  • This paper describes the design of I/Q channel 12bit Digital-to-Analog Converter(DAC) which shows the conversion rate of 120MHz and the power supply of 3.3V with 0.35um CMOS n-well 1-poly 4-metal process for advanced wireless transceiver. The proposed DAC utilizes 4-bit thermometer decoder with 3 stages for minimum glitch energy and linearity error. Also, using a optimized 4bit thermometer decoder for the decrement of the chip area. Integral nonlinearity(INL) of ${\pm}1.6LSB$ and differential nonlinearity(DNL) of ${\pm}1.3LSB$ have been measured. In single tone test, the ENOB of the proposed 12bit DAC is 10.5bit and SFDR of 73dB(@ Fs=120MHz, Fin=1MHz) is measured, respectively. Dual-tone test SFDR is 61 dB (@ Fs=100MHz, Fin=1.5MHz, 2MHz). Glitch energy of 31 pV.s is measured. The converter consumes a total of 105mW from 3.3-V power supply.