• 한국결정성장학회지
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• 제27권6호
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• pp.275-281
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• 2017

AlN는 넓은 밴드 갭 및 높은 열전도율로 인해 넓은 밴드 갭 및 고주파 전자 소자로 유망한 재료이다. AlN은 전력 반도체의 재료로서 더 큰 항복전압과 고전압에서의 더 작은 특성저항의 장점을 가지고 있다. 높은 전도도를 갖는 p형 AlN 에피층의 성장은 AlN 기반 응용 제품 제조에 중요하다. 본 논문에서는 Mg이 도핑된 AlN 에피층을 혼합 소스 HVPE에 의해 성장하였다. Al 및 Mg 혼합 금속은 Mg-doped AlN 에피 층의 성장을 위한 소스 물질로 사용하였다. AlN 내의 Mg 농도는 혼합 소스에서 Mg 첨가 질량의 양을 조절함으로써 제어되었다. 다양한 Mg 농도를 갖는 AlN 에피 층의 표면 형태 및 결정 구조는 FE-SEM 및 HR-XRD에 의해 조사하였다. Mg-doped AlN 에피 층의 XPS 스펙트럼으로 부터 혼합 소스 HVPE에 의해 Mg을 AlN 에피 층에 도핑할 수 있음을 증명하였다.

• 센서학회지
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• 제2권1호
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• pp.101-108
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• 1993

컬러센서를 위한 $TiO_{2}$/Se : Te 이종접합을 고주파 반응성 스퍼터링법과 진공증착법을 이용하여 제작하였다. 제조된 $TiO_{2}$ 막형성의 최적조건은 $1000{\AA}$의 $TiO_{2}$ 두께에서 고주파전력 120 W, 기판온도 $100^{\circ}C$, 산소농도 50% 및 분위기압 50 mTorr였다. 이 때 광투과율은 파장 550 nm에서 85%, 저항률은 $2{\times}10^9{\Omega}{\cdot}cm$, 굴절률은 2.3이었다. 제조된 $TiO_{2}$막은 직접천이형 에너지 밴드구조를 가지며 광학적 밴드갭은 3.58 eV였다. 제조된$TiO_{2}$막을 $400^{\circ}C$에서 30분간 열처리함으로써 광투과율이 파장 $300{\sim}580$ nm범위에서 $0{\sim}25%$까지 개선되었다. 또한 화학양론적 조성비를 조사하기 위하여 AES 분석을 한 결과 Ti 및 0의 조성비는 1 : 1.7로 나타났다. 한편 Se : Te 막형성의 최적조건은 $190^{\circ}C$에서 1분간 열처리했을 때였다. 이러한 조건으로 제조된 Se : Te막의 광학적 밴드갭은 1.7 eV였으며 육방정계구조의 (100) 방향 및 (110) 방향으로 Se : Te 막이 결정화됨을 알 수 있었다. 1000 lux의 조도에서 Se : Te막의 광전변환률은 0.75였다. 또한 Se에 Te를 첨가함으로써 장파장영역의 분광감도가 향상되었다. $TiO_{2}$/Se : Te 이종접합의 분광감도는 가시광 전영역에서 비교적 넓은 분광감도를 나타내었으며, 특히 청색영역에서 a-Si박막보다 우수한 분광감도를 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

• 전기화학회지
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• 제18권1호
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• pp.17-23
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• 2015

$Li_4Ti_5O_{12}$는 우수한 안정성으로 자동차용 리튬 이온 이차전지의 음극 활물질로서 각광 받고 있다. 그러나 넓은 밴드갭에 기인한 절연체 특성으로 고율 충/방전을 가능하게 하기 위해서는 전자 전도도의 개선이 필수적이다. 본 연구에서는 Cr 도핑을 통해 $Li_4Ti_5O_{12}$의 전자 전도도 개선을 목표로 하였으며, wet-mixing법을 통한 물질 합성시 도판트인 Cr 프리커서의 용해도 차이에 의한 Cr-doped $Li_4Ti_5O_{12}$의 전기화학적 특성 변화를 고찰하고자 하였다. 시료의 물리적 특성은 ICP, XRD, SEM, EXAFS을 통하여 확인하였고 1.0V~3.0V (vs. $Li/Li^+$) 하에서 충/방전 특성을 조사하였다. 프리커서의 용해도는 합성된 물질의 상(phase) 및 모폴로지에 큰 영향을 미쳤으며, 가장 용해도가 높은 $Cr(NO_3)_2$ 프리커서로부터 합성된 경우 Bare $Li_4Ti_5O_{12}$와 비교하여 약 2배 개선된 고율 충/방전 특성(130 mAh/g @ 10 C)을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.11-11
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• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

• 한국재료학회지
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• 제20권12호
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• pp.676-680
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• 2010

Most TCOs such as ITO, AZO(Al-doped ZnO), FTO(F-doped $SnO_2$) etc., which have been widely used in LCD, touch panel, solar cell, and organic LEDs etc. as transparent electrode material reveal n-type conductivity. But in order to realize transparent circuit, transparent p-n junction, and introduction of transparent p-type materials are prerequisite. Additional prerequisite condition is optical transparency in visible spectral region. Oxide based materials usually have a wide optical bandgap more than ~3.0 eV. In this study, single-phase transparent semiconductor of $SrCu_2O_2$, which shows p-type conductivity, have been synthesized by 2-step solid state reaction at $950^{\circ}C$ under $N_2$ atmosphere, and single-phase $SrCu_2O_2$ thin films of p-type TCOs have been deposited by RF magnetron sputtering on alkali-free glass substrate from single-phase target at $500^{\circ}C$, 1% $H_2$/(Ar + $H_2$) atmosphere. 3% $H_2$/(Ar + $H_2$) resulted in formation of second phases. Hall measurements confirmed the p-type nature of the fabricated $SrCu_2O_2$ thin films. The electrical conductivity, mobility of carrier and carrier density $5.27{\times}10^{-2}S/cm$, $2.2cm^2$/Vs, $1.53{\times}10^{17}/cm^3$ a room temperature, respectively. Transmittance and optical band-gap of the $SrCu_2O_2$ thin films revealed 62% at 550 nm and 3.28 eV. The electrical and optical properties of the obtained $SrCu_2O_2$ thin films deposited by RF magnetron sputtering were compared with those deposited by PLD and e-beam.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.142.2-142.2
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• 2018

One-dimensional metal oxide nanostructures have attracted considerable research activities owing to their strong application potential as components for nanosize electronic or optoelectronic devices utilizing superior optical and electrical properties. In which, semiconducting $SnO_2$ material with wide-bandgap Eg = 3.6 eV at room temperature, is one of the attractive candidates for optoelectronic devices operating at room temperature [1, 2], gas sensor [3, 4], and transparent conducting electrodes [5]. The synthesis and gas sensing properties of semiconducting $SnO_2$ nanomaterials have become one of important research issues since the first synthesis of SnO2 nanowires. In this study, $SnO_2$ nanowire networks were synthesized on a basis of a two-step process. In step 1, Sn spheres (30-800 nm in diameter) embedded in $SiO_2$ on a Si substrate was synthesized by a chemical vapor deposition method at $700^{\circ}C$. In step 2, using the source of these Sn spheres, $SnO_2$ nanowire (20-40 nm in diameter; $1-10{\mu}m$ in length) networks on a spherical Sn surface were synthesized by a thermal oxidation method at $800^{\circ}C$. The Au layers were pre-deposited on the surface of Sn spherical and subsequently oxidized Sn surface of Sn spherical formed SnO2 nanowires networks. Field emission scanning electron microscopy and high-resolution transmission electron microscopy images indicated that $SnO_2$ nanowires are single crystalline. In addition, the $SnO_2$ nanowire is also a tetragonal rutile, with the preferred growth directions along [100] and a lattice spacing of 0.237 nm. Subsequently, the $NO_2$ sensing properties of the $SnO_2$ network nanowires sensor at an operating temperature of $50-250^{\circ}C$ were examined, and showed a reversible response to $NO_2$ at various $NO_2$ concentrations. Finally, details of the growth mechanism and formation of Sn spheres and $SnO_2$ nanowire networks are also discussed.

• 한국결정성장학회지
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• 제25권4호
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• pp.127-134
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• 2015

AlN 단결정은 넓은 밴드갭(6.2 eV), 높은 열 전도도($285W/m{\cdot}K$), 높은 비저항(${\geq}10^{14}{\Omega}{\cdot}cm$), 그리고 높은 기계적 강도와 같은 장점들 때문에 차세대 반도체 적용을 위한 많은 흥미를 끈다. 벌크 AlN 단결정 또는 박막 템플릿(template)들은 주로 PVT(Physical vapor transport)법, 플럭스(flux)법, 용액 성장(solution growth)법, 그리고 증기 액상 증착(HVPE)법에 의해 성장된다. 단결정이 성장하는 동안에 발생하는 결함들 때문에 상업적으로 어려움을 갖게 된 이후로 결함들 분석을 통한 결정 품질 향상은 필수적이다. 격자결함 밀도(EPD)분석은 AlN 표면에 입자간 방위차와 결함이 존재하고 있는 것을 보여준다. 투과전자현미경(TEM)과 전자후방산란회절(EBSD)분석은 전체적인 결정 퀄리티와 다양한 결함의 종류들을 연구하는데 사용된다. 투과전자현미경(TEM)관찰로 AlN의 형태가 적층 결함, 전위, 이차상 등에 의해 크게 영향을 받는 것을 알 수 있었다. 또한 전자후방산란회절(EBSD)분석은 전위의 생성을 유도하는 성장 결함으로서 AlN의 zinc blende 폴리모프(polymorph)가 존재하고 있는 것을 나타내고 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.74-74
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• 2010

One-dimensional nanosturctures such as nanowires and nanotube have been mainly proposed as important components of nano-electronic devices and are expected to play an integral part in design and construction of these devices. Silicon carbide(SiC) is one of a promising wide bandgap semiconductor that exhibits extraordinary properties, such as higher thermal conductivity, mechanical and chemical stability than silicon. Therefore, the synthesis of SiC-based nanowires(NWs) open a possibility for developing a potential application in nano-electronic devices which have to work under harsh environment. In this study, one-dimensional nanowires(NWs) of cubic phase silicon carbide($\beta$-SiC) were efficiently produced by thermal chemical vapor deposition(T-CVD) synthesis of mixtures containing Si powders and hydrocarbon in a alumina boat about $T\;=\;1400^{\circ}C$ SEM images are shown that the temperature below $1300^{\circ}C$ is not enough to synthesis the SiC NWs due to insufficient thermal energy for melting of Si Powder and decomposition of methane gas. However, the SiC NWs are produced over $1300^{\circ}C$ and the most efficient temperature for growth of SiC NWs is about $1400^{\circ}C$ with an average diameter range between 50 ~ 150 nm. Raman spectra revealed the crystal form of the synthesized SiC NWs is a cubic phase. Two distinct peaks at 795 and $970\;cm^{-1}$ over $1400^{\circ}C$ represent the TO and LO mode of the bulk $\beta$-SiC, respectively. In XRD spectra, this result was also verified with the strongest (111) peaks at $2{\theta}=35.7^{\circ}$, which is very close to (111) plane peak position of 3C-SiC over $1400 ^{\circ}C$ TEM images are represented to two typical $\beta$-SiC NWs structures. One is shown the defect-free $\beta$-SiC nanowire with a (111) interplane distance with 0.25 nm, and the other is the stacking-faulted $\beta$-SiC nanowire. Two SiC nanowires are covered with $SiO_2$ layer with a thickness of less 2 nm. Moreover, by changing the flow rate of methane gas, the 300 sccm is the optimal condition for synthesis of a large amount of $\beta$-SiC NWs.

• 한국전기전자재료학회논문지
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• 제35권6호
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• pp.603-609
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• 2022

Passivation quality is mainly governed by epitaxial growth of crystalline silicon wafer surface. Void-rich intrinsic a-Si:H interfacial layer could offer higher resistivity of the c-Si surface and hence a better device efficiency as well. To reduce the resistivity of the contact area, a modification of void-rich intrinsic layer of a-Si:H towards more ordered state with a higher density is adopted by adapting its thickness and reducing its series resistance significantly, but it slightly decreases passivation quality. Higher resistance is not dominated by asymmetric effects like different band offsets for electrons or holes. In this study, multilayer of intrinsic a-Si:H layers were used. The first one with a void-rich was a-Si:H(I₁) and the next one a-SiO_x:H(I₂) were used, where a-SiO_x:H(I₂) had relatively larger band gap of ~2.07 eV than that of a-Si:H (I₁). Using a-SiO_x:H as I₂ layer was expected to increase transparency, which could lead to an easy carrier transport. Also, higher implied voltage than the conventional structure was expected. This means that the a-SiO_x:H could be a promising material for a high-quality passivation of c-Si. In addition, the i-a-SiO_x:H microstructure can help the carrier transportation through tunneling and thermal emission.